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公开(公告)号：US20220029660A1
公开(公告)日：2022-01-27
申请号：US17385122
申请日：2021-07-26
Inventor： Marc Houdebine , Kosta Kovacic , Florent Sibille
Abstract: An embodiment device comprises a phase locked loop and a frequency locked loop having in common the same controlled oscillator. The device is firstly placed in the card emulation mode at the beginning of a communication between the contactless communication device and a contactless reader, the firstly placing comprising synchronizing within the contactless device, an ALM carrier frequency with a reader carrier frequency by operating at least the phase locked loop, and upon reception by the contactless communication device of an indication sent by the reader indicating a further communication in a peer to peer mode with the reader, the device is secondly placed in the peer to peer mode, the secondly placing including deactivating the phase locked loop and operating the frequency locked loop with a reference clock signal and a frequency set point depending on the reader carrier frequency and the frequency of the reference clock signal.
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公开(公告)号：US20210126672A1
公开(公告)日：2021-04-29
申请号：US17080431
申请日：2020-10-26
Applicant: STMicroelectronics SA
Inventor： Marc Houdebine , Laurent Jean Garcia
Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.
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3.发明申请公开(公告)号：US20190230611A1
公开(公告)日：2019-07-25
申请号：US16250443
申请日：2019-01-17
Applicant: STMicroelectronics SA
Inventor： Marc Houdebine
Abstract: Data frames, including bursts of an active load modulation (ALM) carrier signal generated from a modulation of an underlying carrier, are transmitted from an object to a reader. Synchronizing a reader carrier signal and the ALM carrier signal includes: prior to transmission of each data frame and between some of the bursts of the ALM carrier signal of each data frame, performing a closed-loop control of an output signal of a main oscillator onto a phase and a frequency of the reader carrier signal; estimating a ratio between a frequency of the output signal of the main oscillator and a frequency of a reference signal produced by a reference oscillator; and during each burst of the ALM carrier signal of each data frame, performing a closed-loop control in frequency only of the output signal of the main oscillator onto the reference frequency of the reference signal corrected by the ratio.
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公开(公告)号：US20240014809A1
公开(公告)日：2024-01-11
申请号：US18345726
申请日：2023-06-30
Applicant: STMicroelectronics SA
Inventor： Laurent Jean Garcia , Marc Houdebine
IPC: H03K3/03 , H03K5/1252
CPC classification number: H03K3/0315 , H03K5/1252
Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
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5.发明申请公开(公告)号：US20200099554A1
公开(公告)日：2020-03-26
申请号：US16569999
申请日：2019-09-13
Applicant: STMicroelectronics SA
Inventor： Marc Houdebine
IPC: H04L27/00
Abstract: A method of contactless communication can be performed between an object and a reader using active load modulation. A synchronization process is performed between a first carrier signal transmitted by the reader and having a reference frequency, and a second carrier signal extracted from an output signal of a controlled oscillator of a digital phase-locked loop of the object. In the synchronization process, as long as a locking of the loop has not been detected, the frequency of the output signal of the oscillator is latched on a frequency that is a multiple of the reference frequency. Once the locking has been detected, the latching continues while controlling the oscillator with a second control signal generated from a second value obtained.
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Patent Agency Ranking
公开(公告)号：US10560255B2
公开(公告)日：2020-02-11
申请号：US16029457
申请日：2018-07-06
Inventor： Maksimiljan Stiglic , Nejc Suhadolnik , Marc Houdebine
Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.
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公开(公告)号：US10261117B2
公开(公告)日：2019-04-16
申请号：US15139801
申请日：2016-04-27
Applicant: STMICROELECTRONICS SA
Inventor： Marc Houdebine , Sebastien Dedieu
Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.
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8.发明授权公开(公告)号：US10135451B2
公开(公告)日：2018-11-20
申请号：US15800302
申请日：2017-11-01
Applicant: STMicroelectronics SA
Inventor： Marc Houdebine , Sebastien Dedieu
Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.
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9.发明申请公开(公告)号：US20180269886A1
公开(公告)日：2018-09-20
申请号：US15800302
申请日：2017-11-01
Applicant: STMicroelectronics SA
Inventor： Marc Houdebine , Sebastien Dedieu
CPC classification number: H03L7/1974 , H03K5/00006 , H03L7/0891 , H03L7/1976 , H03L2207/10 , H04L7/0331
Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.
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10.发明授权公开(公告)号：US09998178B2
公开(公告)日：2018-06-12
申请号：US15436826
申请日：2017-02-19
Applicant: STMicroelectronics SA
Inventor： Sebastien Dedieu , Marc Houdebine
CPC classification number: H04B5/0031 , G06K7/10297 , H03L7/08 , H03L7/081 , H03L7/093 , H03L7/099 , H03L7/14 , H03L7/23 , H04B5/0056 , H04B5/0062 , H04B5/0093 , H04W4/80
Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.
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