公开(公告)号：US20140373640A1

公开(公告)日：2014-12-25

申请号：US14311497

申请日：2014-06-23

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vincent FIORI ,  Pierre BAR ,  Sébastien GALLOIS-GARREIGNOT

IPC: G01L1/20

CPC classification number: G01L1/20 ,  G01B7/18 ,  G01L1/2287 ,  G01L5/161 ,  G01L25/00 ,  H01L22/34

Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.

Abstract translation: 提供了一种用于确定具有平坦表面的物体的三维应力场的方法和相应的系统。 至少四个扁平电阻器被放置在物体的平坦表面上，其中至少一个电阻器的几何形状与其他几何形状不同。 测量电阻的电阻变化。 三维应力场由涉及应力场的方程组，测量的电阻值的变化值和电阻的灵敏度参数确定。

公开(公告)号：US20200211835A1

公开(公告)日：2020-07-02

申请号：US16709251

申请日：2019-12-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia RISTOIU ,  Pierre BAR ,  Francois LEVERD

IPC: H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US20230005735A1

公开(公告)日：2023-01-05

申请号：US17940758

申请日：2022-09-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia RISTOIU ,  Pierre BAR ,  Francois LEVERD

IPC: H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US20190214270A1

公开(公告)日：2019-07-11

申请号：US16240044

申请日：2019-01-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre BAR ,  Francois LEVERD ,  Delia RISTOIU

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31144 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/42 ,  H01L21/02507 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.