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    DISPLAY DEVICE
    3.
    发明申请
    DISPLAY DEVICE 审中-公开
    显示设备

    公开(公告)号：US20170039965A1

    公开(公告)日：2017-02-09

    申请号：US15332827

    申请日：2016-10-24

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Nam-Soo KANG ,  Seong-Young LEE ,  Sung-Man KIM ,  Seung-Hwan MOON

    IPC: G09G3/36

    CPC classification number: G09G3/3614 ,  G02F1/136286 ,  G09G3/36 ,  G09G3/3611 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0247

    Abstract: A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

    Abstract translation: 显示装置包括具有像素行和像素列的像素矩阵，并且包括具有切换元件的像素，交替元件交替地位于每个像素列的上侧和下侧附近的角落处，并且交替地位于靠近上侧和下侧的拐角处， 交替地在每个像素列的左侧和右侧的角落处; 多对栅极线传输栅极导通电压; 和多条数据线传输数据电压，其中每对栅极线设置在每个像素行的上侧和下侧，每行中的像素连接到最靠近各个开关元件的栅极线，并且每条数据线被布置 在相邻的像素列对之间并连接到成对的像素对，其中该对的一个像素具有位于最靠近相应数据线的开关元件。

    DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME
    4.
    发明申请
    DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME 有权
    显示基板，其制造方法和具有该基板的显示装置

    公开(公告)号：US20150200145A1

    公开(公告)日：2015-07-16

    申请号：US14312912

    申请日：2014-06-24

    Applicant: Samsung Display Co., LTD.

    Inventor： Dong-Hyun YOO ,  Seong-Young LEE ,  Jae-Won KIM ,  Hyung-Jun PARK

    IPC: H01L21/66 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L21/3213

    CPC classification number: H01L22/32 ,  G02F1/1309 ,  G02F1/136259 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136254 ,  G09G3/006 ,  G09G3/3648 ,  H01L21/32133 ,  H01L27/124 ,  H01L27/1259

    Abstract: A display substrate includes a base substrate including a display area and a peripheral area surrounding the display area, a switching element in the display area, a main-test-line in the peripheral area, extending in the second direction and electrically connected with a data line, a sub-test-line in the peripheral area, and a test pad in the peripheral area and electrically connected with the main-test-line and the sub-test-line. The switching element is electrically connected with a gate line extending in a first direction and the data line extending in a second direction crossing the first direction. The sub-test-line is electrically connected with the data line. The sub-test-line is in a different layer from the main-test-line.

    Abstract translation: 显示基板包括：基板，包括显示区域和围绕显示区域的外围区域;显示区域中的开关元件;外围区域中的主测试线，沿第二方向延伸并与数据电连接 线路，外围区域中的子测试线以及周边区域中的测试焊盘，并与主测试线和副测试线电连接。 开关元件与沿第一方向延伸的栅极线电连接，数据线沿与第一方向交叉的第二方向延伸。 子测试线与数据线电连接。 子测试线与主测试线不同。

    DRIVING UNIT AND DISPLAY DEVICE HAVING THE SAME
    5.
    发明申请
    DRIVING UNIT AND DISPLAY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20170256226A1

    公开(公告)日：2017-09-07

    申请号：US15601026

    申请日：2017-05-22

    Applicant: Samsung Display Co., Ltd.

    Inventor： Haeng-Won PARK ,  Seung-Hwan MOON ,  Nam-Soo KANG ,  Sung-Jae MOON ,  Sung-Man KIM ,  Seong-Young LEE ,  Yong-Soon LEE

    IPC: G09G3/36 ,  G11C19/18

    CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

    Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

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