Spatial memory streaming confidence mechanism

    公开(公告)号:US10540287B2

    公开(公告)日:2020-01-21

    申请号:US15690931

    申请日:2017-08-30

    Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

    Address re-ordering mechanism for efficient pre-fetch training in an out-of order processor

    公开(公告)号:US10031851B2

    公开(公告)日:2018-07-24

    申请号:US15401515

    申请日:2017-01-09

    Abstract: A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

    Pre-fetch chaining
    7.
    发明授权
    Pre-fetch chaining 有权
    预取链接

    公开(公告)号:US09569361B2

    公开(公告)日:2017-02-14

    申请号:US14325343

    申请日:2014-07-07

    CPC classification number: G06F12/0862 G06F12/10 G06F2212/6022

    Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.

    Abstract translation: 根据一个一般方面,设备可以包括高速缓存预取器和预取调度器。 高速缓存预取器可以被配置为至少部分地基于虚拟地址预测要从存储器系统检索的数据。 预取调度器可以被配置为将数据的虚拟地址转换为数据的物理地址,并且从存储器系统的多个级别之一请求数据。 存储器系统可以包括多个级别,存储器系统的每个级别被配置为存储数据。

    ADDRESS RE-ORDERING MECHANISM FOR EFFICIENT PRE-FETCH TRAINING IN AN OUT-OF-ORDER PROCESSOR
    8.
    发明申请
    ADDRESS RE-ORDERING MECHANISM FOR EFFICIENT PRE-FETCH TRAINING IN AN OUT-OF-ORDER PROCESSOR 有权
    寻求在订单处理器中进行有效预先培训的重新订购机制

    公开(公告)号:US20150278100A1

    公开(公告)日:2015-10-01

    申请号:US14498878

    申请日:2014-09-26

    Abstract: A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

    Abstract translation: 计算系统包括:指令调度模块,被配置为接收程序指令; 耦合到指令调度模块的地址重排序模块,被配置为当所述程序指令是预取过滤器中的高速缓存行中的命中时对所述程序指令进行过滤。 计算机系统还包括:指令调度模块,被配置为接收程序指令; 一个地址重排序模块,耦合到指令调度模块,被配置为:以程序顺序在程序指令的标签模块中分配标签,在虚拟地址模块中为程序指令分配虚拟地址, 相对于程序顺序的顺序,并插入与标签相关联的指针,以将标签链接到虚拟地址。

    SPATIAL MEMORY STREAMING CONFIDENCE MECHANISM

    公开(公告)号:US20180329822A1

    公开(公告)日:2018-11-15

    申请号:US15690931

    申请日:2017-08-30

    Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

    Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor
    10.
    发明授权
    Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor 有权
    解决无序处理器中高效预取训练的重新排序机制

    公开(公告)号:US09542323B2

    公开(公告)日:2017-01-10

    申请号:US14498878

    申请日:2014-09-26

    Abstract: A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

    Abstract translation: 计算系统包括:指令调度模块,被配置为接收程序指令; 耦合到指令调度模块的地址重排序模块,被配置为当所述程序指令是预取过滤器中的高速缓存行中的命中时对所述程序指令进行过滤。 计算机系统还包括:指令调度模块,被配置为接收程序指令; 一个地址重排序模块,耦合到指令调度模块,被配置为:以程序顺序在程序指令的标签模块中分配标签,在虚拟地址模块中为程序指令分配虚拟地址, 相对于程序顺序的顺序,并插入与标签相关联的指针,以将标签链接到虚拟地址。

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