公开(公告)号：US20240213249A1

公开(公告)日：2024-06-27

申请号：US18512094

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHOON HWANG ,  KYUNGHO KIM ,  BYUNGHO MOON ,  KYUNGHEE CHO ,  DOYOUNG CHOI ,  INCHAN HWANG

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.

公开(公告)号：US20240347609A1

公开(公告)日：2024-10-17

申请号：US18500499

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  HYOJIN KIM ,  BYUNGHO MOON ,  MYUNGIL KANG ,  WOOSEOK PARK ,  JAEHO JEON

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, first and second source/drain patterns overlapping with the active pattern, a separation insulating layer between the first and second source/drain patterns, and first and second gate electrodes spaced apart from each other with the separation insulating layer interposed therebetween. A level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode.