公开(公告)号：US20240213249A1

公开(公告)日：2024-06-27

申请号：US18512094

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHOON HWANG ,  KYUNGHO KIM ,  BYUNGHO MOON ,  KYUNGHEE CHO ,  DOYOUNG CHOI ,  INCHAN HWANG

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.

公开(公告)号：US20240105724A1

公开(公告)日：2024-03-28

申请号：US18196741

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  MYUNGIL KANG ,  MINCHAN GWAK ,  Kyungho KIM ,  Kyung Hee CHO ,  DOYOUNG CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.

公开(公告)号：US20240347609A1

公开(公告)日：2024-10-17

申请号：US18500499

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  HYOJIN KIM ,  BYUNGHO MOON ,  MYUNGIL KANG ,  WOOSEOK PARK ,  JAEHO JEON

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, first and second source/drain patterns overlapping with the active pattern, a separation insulating layer between the first and second source/drain patterns, and first and second gate electrodes spaced apart from each other with the separation insulating layer interposed therebetween. A level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode.

公开(公告)号：US20240145567A1

公开(公告)日：2024-05-02

申请号：US18329830

申请日：2023-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INCHAN HWANG ,  MYUNGIL KANG ,  DONGHOON HWANG ,  KYUNGHO KIM ,  SUNGWOO JANG ,  KYUNG HEE CHO

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes: an active area that protrudes from an upper surface of a substrate and extends parallel to the upper surface of the substrate; an element isolating area formed on the substrate and around the active area; a channel formed on an upper surface of the active area; a gate structure that surrounds at least two surfaces of the channel; a spacer formed on both sidewalls of the gate structure; and a source/drain layer in contact with both sidewalls of the channel and insulated from the gate structure by the spacer. The gate structure includes, in a cross-section, a first portion whose width in a first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose width in the first direction remains the same or decreases below the first portion.