公开(公告)号：US20230387205A1

公开(公告)日：2023-11-30

申请号：US18100233

申请日：2023-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hwan KIM ,  KYUNGHO KIM ,  KANG HUN MOON ,  CHOEUN LEE ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/6656

Abstract: A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.

公开(公告)号：US20240213249A1

公开(公告)日：2024-06-27

申请号：US18512094

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHOON HWANG ,  KYUNGHO KIM ,  BYUNGHO MOON ,  KYUNGHEE CHO ,  DOYOUNG CHOI ,  INCHAN HWANG

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.

公开(公告)号：US20240145567A1

公开(公告)日：2024-05-02

申请号：US18329830

申请日：2023-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INCHAN HWANG ,  MYUNGIL KANG ,  DONGHOON HWANG ,  KYUNGHO KIM ,  SUNGWOO JANG ,  KYUNG HEE CHO

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes: an active area that protrudes from an upper surface of a substrate and extends parallel to the upper surface of the substrate; an element isolating area formed on the substrate and around the active area; a channel formed on an upper surface of the active area; a gate structure that surrounds at least two surfaces of the channel; a spacer formed on both sidewalls of the gate structure; and a source/drain layer in contact with both sidewalls of the channel and insulated from the gate structure by the spacer. The gate structure includes, in a cross-section, a first portion whose width in a first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose width in the first direction remains the same or decreases below the first portion.

公开(公告)号：US20230402535A1

公开(公告)日：2023-12-14

申请号：US18081855

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHO KIM ,  KI HWAN KIM ,  KANG HUN MOON ,  CHOEUN LEE ,  YONGUK JEON

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/41775

Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of spaced apart and vertically stacked semiconductor patterns, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent ones of the plurality of semiconductor patterns, and an inner spacer interposed between the portion of the gate electrode and the source/drain pattern, wherein the inner spacer is crystalline metal oxide is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga.