公开(公告)号：US11995391B2

公开(公告)日：2024-05-28

申请号：US17702879

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongdeok Kim ,  Munjun Seo ,  Bonghyun Lee

IPC: G06F30/392 ,  G03F1/36 ,  G06F30/3953 ,  G06F30/398

CPC classification number: G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US11776950B2

公开(公告)日：2023-10-03

申请号：US17951381

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonghyun Lee

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5286 ,  H01L27/0924

Abstract: An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.

公开(公告)号：US11495592B2

公开(公告)日：2022-11-08

申请号：US17136754

申请日：2020-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonghyun Lee

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528 ,  H01L27/092

Abstract: An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.

公开(公告)号：US11646305B2

公开(公告)日：2023-05-09

申请号：US16946620

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungok Lee ,  Sangdo Park ,  Jun Seomun ,  Bonghyun Lee

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0207

Abstract: Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

公开(公告)号：US20220129612A1

公开(公告)日：2022-04-28

申请号：US17238874

申请日：2021-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonghyun Lee

IPC: G06F30/396 ,  H01L23/528

Abstract: A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.

公开(公告)号：US11314919B2

公开(公告)日：2022-04-26

申请号：US17022233

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongdeok Kim ,  Munjun Seo ,  Bonghyun Lee

IPC: G06F30/30 ,  G06F30/3953 ,  G03F1/36 ,  G06F30/398 ,  G06F30/392

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US12056430B2

公开(公告)日：2024-08-06

申请号：US17238874

申请日：2021-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonghyun Lee

IPC: G06F30/396 ,  H01L23/528 ,  G06F117/04

CPC classification number: G06F30/396 ,  H01L23/5286 ,  G06F2117/04

Abstract: A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.

公开(公告)号：US11387229B2

公开(公告)日：2022-07-12

申请号：US16826756

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha Lee ,  Ha-Young Kim ,  Bonghyun Lee ,  Soyoung Lee ,  Yongeun Cho

IPC: H01L29/76 ,  H01L27/02 ,  G06F30/398 ,  G06F30/394 ,  G06F30/392

Abstract: Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

公开(公告)号：US20250098295A1

公开(公告)日：2025-03-20

申请号：US18817500

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kibum Nam ,  Bonghyun Lee

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit comprising: a plurality of first gate electrodes extending in a second direction perpendicular to a first direction, wherein the plurality of first gate electrodes is in a first row that extends in the first direction; a first active pattern group comprising a plurality of first active patterns that extend in the first row in the first direction and intersecting the plurality of first gate electrodes; a plurality of second gate electrodes extending in the second direction in a second row that extends in the first direction; and a second active pattern group comprising a plurality of second active patterns extending in the second row in the first direction and intersecting the plurality of second gate electrodes, wherein ones of the plurality of first active patterns have different widths in the second direction, and the plurality of second active patterns have a first width in the second direction.

公开(公告)号：US11727184B2

公开(公告)日：2023-08-15

申请号：US17877483

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonghyun Lee ,  Jungho Do

IPC: G06F30/00 ,  G06F30/392 ,  H01L23/528 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L23/5286 ,  H01L27/0207

Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.