公开(公告)号：US20210383735A1

公开(公告)日：2021-12-09

申请号：US17139449

申请日：2020-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmok KIM ,  Kyunglyong KANG ,  Jungu KANG ,  Boyoung SEO ,  Yongsang JEONG

IPC: G09G3/20

Abstract: A display apparatus includes a display panel; and a display driver integrated circuit (DDI) chip coupled to the display panel, the DDI chip being configured to generate a display driving signal for driving the display panel based on image data. The DDI chip may include: a first embedded memory device embedded in the DDI chip and configured to store compensation data for compensating for electrical and optical characteristics of a plurality of pixels included in the display panel; a timing controller configured to control signals for driving the display panel, and to generate a data control signal based on the image data and the compensation data; and a data driver configured to provide a data voltage to the display panel according to the data control signal. The first embedded memory device may not include static random access memory (SRAM).

公开(公告)号：US20220261625A1

公开(公告)日：2022-08-18

申请号：US17474466

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangho LEE ,  Boyoung SEO ,  Sangjoon KIM ,  Seungchul JUNG

IPC: G06N3/063 ,  G11C11/16

Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

公开(公告)号：US20250166702A1

公开(公告)日：2025-05-22

申请号：US18947724

申请日：2024-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyuk LEE ,  Soon-Wan KWON ,  Sang Joon KIM ,  Sungmeen MYUNG ,  Boyoung SEO ,  Seok Ju YUN ,  Kangho LEE

IPC: G11C13/00

Abstract: A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.

公开(公告)号：US20190259437A1

公开(公告)日：2019-08-22

申请号：US16285295

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

IPC: G11C11/16 ,  H01L27/22

Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

公开(公告)号：US20190198077A1

公开(公告)日：2019-06-27

申请号：US16290102

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung SEO ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  G11C17/02

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.