公开(公告)号：US20190259439A1

公开(公告)日：2019-08-22

申请号：US16405219

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Hoon JEON ,  Yong Seok KIM ,  Jun Hee LIM

IPC: G11C11/40 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/8238 ,  H01L27/092 ,  G11C16/04 ,  H01L21/8234

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

公开(公告)号：US20180358079A1

公开(公告)日：2018-12-13

申请号：US15794628

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Hoon JEON ,  Yong Seok KIM ,  Jun Hee LIM

IPC: G11C11/40

CPC classification number: G11C11/40

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors, The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

公开(公告)号：US20190267088A1

公开(公告)日：2019-08-29

申请号：US16059317

申请日：2018-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Hoon JEON ,  Yoo Cheol Shin ,  Jun Hee Lim ,  Sung Kweon Baek ,  Chan Ho Lee ,  Won Chul Jang ,  Sun Gyung Hwang

IPC: G11C14/00 ,  G11C11/401 ,  H01L27/108 ,  H01L23/532

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.