公开(公告)号：US20180151561A1

公开(公告)日：2018-05-31

申请号：US15489093

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco CANTORO ,  Yeon Cheol HEO ,  Byoung Gi KIM ,  Chang Min YOE ,  Seung Chan YUN ,  Dong Hun LEE ,  Yun Il LEE ,  Hyung Suk LEE

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/50 ,  H01L21/8234

CPC classification number: H01L27/088 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823487 ,  H01L23/50 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.

公开(公告)号：US20240413203A1

公开(公告)日：2024-12-12

申请号：US18543414

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Min YOE ,  Ji Wang KO ,  Jae Hong CHOI ,  Jun Ho HONG ,  Dong Min KIM ,  Jeong Min CHOI

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern is on the substrate and extends in a first horizontal direction. First to third nanosheets are sequentially stacked on the active pattern and are spaced apart from each other in a vertical direction. A gate electrode is on the active pattern and extends in a second horizontal direction. The gate electrode surrounds each of the first to third nanosheets. A source/drain region is on the active pattern on at least one side of the gate electrode. An interlayer insulating layer covers the source/drain region. A source/drain contact penetrates the interlayer insulating layer in the vertical direction and is connected to the source/drain region. At least a portion of the interlayer insulating layer is disposed between sidewalls of the source/drain contact and the source/drain region in the first horizontal direction and overlaps sidewalls of the third nanosheet along the first horizontal direction.