公开(公告)号：US20160293622A1

公开(公告)日：2016-10-06

申请号：US15054428

申请日：2016-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Woon JEONG ,  Jihye KIM ,  Joowon PARK

IPC: H01L27/115

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.

Abstract translation: 三维半导体器件包括在包括第一区域和第二区域的衬底上的电极结构，所述电极结构包括接地选择电极，电池电极和串选择电极，所述接地选择电极，电池电极和串选择电极依次堆叠在所述衬底上， 选择电极，电池电极和串选择电极分别包括在衬底的第二区域中限定阶梯结构的接地选择焊盘，电池焊盘和串选择焊盘，穿过每个电池的多个虚拟柱 电极结构的一部分，以及与每个电极焊盘电连接的电池接触插塞，其中每个虚拟柱穿透相邻的电极焊盘之间的边界，并且其中相邻的电极焊盘共享 虚拟柱子。

公开(公告)号：US20200083242A1

公开(公告)日：2020-03-12

申请号：US16682133

申请日：2019-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Woon JEONG ,  Jihye KIM ,  Joowon PARK

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.

公开(公告)号：US20200075101A1

公开(公告)日：2020-03-05

申请号：US16659715

申请日：2019-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US20190019804A1

公开(公告)日：2019-01-17

申请号：US16136438

申请日：2018-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Woon JEONG ,  Jihye KIM ,  Joowon PARK

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.

公开(公告)号：US20170352674A1

公开(公告)日：2017-12-07

申请号：US15684098

申请日：2017-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Woon JEONG ,  Jihye KIM ,  Joowon PARK

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.