公开(公告)号：US20220352389A1

公开(公告)日：2022-11-03

申请号：US17863127

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung KIM ,  Dong-Soo LEE ,  Sang-Yong KIM ,  Jin-Kyu JANG ,  Won-Keun CHUNG ,  Sang-Jin HYUN

IPC: H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US20200035842A1

公开(公告)日：2020-01-30

申请号：US16532645

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung KIM ,  Dong-Soo LEE ,  Sang-Yong KIM ,  Jin-Kyu JANG ,  Won-Keun CHUNG ,  Sang-Jin HYUN

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L27/092 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US20190088798A1

公开(公告)日：2019-03-21

申请号：US16040807

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung KIM ,  Dong-Soo LEE ,  Sang-Yong KIM ,  Jin-Kyu JANG ,  Won-Keun CHUNG ,  Sang-Jin HYUN

IPC: H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/7926 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US20180316225A1

公开(公告)日：2018-11-01

申请号：US15965274

申请日：2018-04-27

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Sung-Ku YEO ,  Sang-Yun KIM ,  Jae-Seok PARK ,  Young-Ho RYU ,  Kang-Yoon LEE ,  Hamed ABBASIZADEH ,  Sang-Wook KWON ,  Thi Kim Nga TRUONG ,  Dong-In KIM ,  Sung-Bum PARK ,  Dong-Soo LEE

IPC: H02J50/12 ,  H02J7/00 ,  H02J7/02 ,  H02J50/70

Abstract: An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

公开(公告)号：US20230187446A1

公开(公告)日：2023-06-15

申请号：US18082617

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Seok JO ,  Jae-Hyun LEE ,  Jong-Han LEE ,  Hong-Bae PARK ,  Dong-Soo LEE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823864 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/823871 ,  H01L29/517

Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.

公开(公告)号：US20210151610A1

公开(公告)日：2021-05-20

申请号：US17134611

申请日：2020-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung KIM ,  Dong-Soo LEE ,  Sang-Yong KIM ,  Jin-Kyu JANG ,  Won-Keun CHUNG ,  Sang-Jin HYUN

IPC: H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US20150179787A1

公开(公告)日：2015-06-25

申请号：US14577478

申请日：2014-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jin CHO ,  Tae-Joo PARK ,  Dong-Soo LEE ,  Myoung-Jae LEE ,  Seong-ho CHO

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/306 ,  H01L29/66795

Abstract: Provided are group III-V semiconductor transistors and methods of manufacturing the same. The method includes forming a group III-V semiconductor channel layer on a substrate, forming a gate insulating layer covering the group III-V semiconductor channel layer, and forming a protection layer including sulfur between the group III-V semiconductor channel layer and the gate insulating layer by annealing the substrate under a sulfur atmosphere.

Abstract translation: 提供III-V族半导体晶体管及其制造方法。 该方法包括在衬底上形成III-V族半导体沟道层，形成覆盖III-V族半导体沟道层的栅极绝缘层，并且在III-V族半导体沟道层和栅极之间形成包含硫的保护层 绝缘层，通过在硫气氛下退火衬底。