公开(公告)号：US20240145556A1

公开(公告)日：2024-05-02

申请号：US18382616

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Hojun Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.

公开(公告)号：US20240055493A1

公开(公告)日：2024-02-15

申请号：US18364521

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Kyoungwoo Lee ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a fin-type active pattern, source/drain regions on the fin-type active pattern, an interlayer insulating layer on the isolation insulating layer, and on the source/drain region, a contact structure electrically connected to the source/drain regions, a buried conductive structure electrically connected to the contact structure and buried in the interlayer insulating layer, and a power delivery structure that penetrates the substrate, and is in contact with a bottom surface of the buried conductive structure. The buried conductive structure includes a first contact plug, and a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom surface of the first contact plug. The power delivery structure includes a second contact plug in direct contact with the bottom surface of the first contact plug.