公开(公告)号：US20240395713A1

公开(公告)日：2024-11-28

申请号：US18582859

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Jungho Do ,  Kyoungwoo Lee ,  Gukhee Kim ,  Minchan Gwak

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes first power lines extending on a substrate in a first direction and spaced apart from each other in a second direction, back side power structures on a lower surface of the substrate, standard cells each including an active pattern, a gate pattern intersecting the active pattern, and contacts, power tap cells between at least some of the standard cells and each including vertical power vias, and second power lines electrically connecting at least some of the first power lines to each other. A first portion of the second power lines may extend onto the power tap cells and a second portion of the second power lines that is different from the first portion may extend onto the standard cells. The power tap cells may be arranged in every three or more rows of the standard cells in the second direction in a zigzag pattern.

公开(公告)号：US20240063221A1

公开(公告)日：2024-02-22

申请号：US18125429

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo Lee ,  Yeonho Park ,  Minchan Gwak ,  Hojun Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66439 ,  H01L29/66545

Abstract: A semiconductor device includes active regions, gate structures intersecting the active regions and including gate electrodes, source/drain regions on the active regions on sides of the gate structures, and a gate isolation structure isolating gate structures, which oppose each other, from each other on a region between the active regions. The gate structures that oppose each other include a first gate structure, a second gate structure opposing the first gate structure, a third gate structure extending in parallel to the first gate structure, and a fourth gate structure opposing the third gate structure and extending in parallel to the second gate structure. The gate isolation structure includes a first isolation structure of a line type extending in the first horizontal direction, and second isolation structures of a hole type penetrating through the first isolation structure between the first and second gate structures and between the third and fourth gate structures.

公开(公告)号：US11837475B2

公开(公告)日：2023-12-05

申请号：US17395030

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemyung Choi ,  Kyoungwoo Lee

IPC: H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0273

Abstract: A method for manufacturing a semiconductor device including forming an insulating structure, forming a hard mask layer on the insulating structure, performing a first etching process to form a first opening at the hard mask layer, forming a first sacrificial pattern in the first opening, forming, on the hard mask layer, a first photoresist pattern including a second opening and a third opening, the second opening exposing a top surface of the first sacrificial pattern, the third opening exposing a top surface of the hard mask layer, and performing a second etching process using the first photoresist pattern as an etch mask may be provided.

公开(公告)号：US20240145556A1

公开(公告)日：2024-05-02

申请号：US18382616

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Hojun Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.

公开(公告)号：US20240128161A1

公开(公告)日：2024-04-18

申请号：US18379083

申请日：2023-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Sangcheol Na ,  Sora You ,  Kyoungwoo Lee ,  Minchan Gwak ,  Youngwoo Kim ,  Jinkyu Kim ,  Seungmin Cha

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is an integrated circuit device including a substrate, a plurality of semiconductor patterns on a first surface of the substrate, a gate electrode extending in a first direction and surrounding the semiconductor patterns, a source/drain region disposed on one side of the gate electrode, a vertical power wiring layer extending in a second direction, a liner structure including a first liner and a second liner, the first liner disposed on a lower portion of a sidewall of the vertical power wiring layer and including a first insulating material, and the second liner disposed on an upper portion of the sidewall of the vertical power wiring layer and including a second insulating material, a first contact disposed on the source/drain region and the vertical power wiring layer, and a back wiring structure disposed on a second surface of the substrate and electrically connected to the vertical power wiring layer.

公开(公告)号：US20240072117A1

公开(公告)日：2024-02-29

申请号：US18307259

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Jeewoong Kim ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Anthony Dongick Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823475 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

公开(公告)号：US11978673B2

公开(公告)日：2024-05-07

申请号：US17537571

申请日：2021-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungwoo Lee ,  Minkwon Choi

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/0332 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/823871 ,  H01L29/66477

Abstract: Disclosed is a semiconductor device fabrication method including forming an interlayer dielectric layer and a lower mask layer on a substrate, forming on the lower mask layer first and second upper mask patterns spaced apart from each other in a first direction, wherein each of the first and second upper mask patterns has a line part extending in a second direction and a first protruding part protruding from the line part, forming a spacer covering sidewalls of the line parts of the first and second upper mask patterns and a filling pattern filling a space between the first protruding parts of the first and second upper mask patterns, etching the lower mask layer to form lower mask patterns, etching the interlayer dielectric layer to form grooves on the interlayer dielectric layer, and forming wiring lines in the grooves.

公开(公告)号：US20240080044A1

公开(公告)日：2024-03-07

申请号：US18461120

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesun Kim ,  Jinhong Park ,  Hwisoo So ,  Kyoungwoo Lee ,  Jinhyo Jung

IPC: H03M13/11

CPC classification number: H03M13/1111

Abstract: The method of detecting a soft error includes copying, in a program loaded into a memory, an original branch command to a copied branch command, executing, by a processor, a first command set comprising the copied branch command, executing, by a processor, a second command set comprising the original branch command, and determining, by a soft error detection circuit, whether an error exists in the execution of the original branch command based on the execution result of the first command set and the second command set.

公开(公告)号：US20240055493A1

公开(公告)日：2024-02-15

申请号：US18364521

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Kyoungwoo Lee ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a fin-type active pattern, source/drain regions on the fin-type active pattern, an interlayer insulating layer on the isolation insulating layer, and on the source/drain region, a contact structure electrically connected to the source/drain regions, a buried conductive structure electrically connected to the contact structure and buried in the interlayer insulating layer, and a power delivery structure that penetrates the substrate, and is in contact with a bottom surface of the buried conductive structure. The buried conductive structure includes a first contact plug, and a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom surface of the first contact plug. The power delivery structure includes a second contact plug in direct contact with the bottom surface of the first contact plug.

公开(公告)号：US20240030326A1

公开(公告)日：2024-01-25

申请号：US18159200

申请日：2023-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sora YOU ,  Kyoungwoo Lee ,  Sungmoon Lee ,  Seungmin Cha ,  Hagju Cho

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/0673

Abstract: A semiconductor device includes parallel active regions on a substrate and extending in a first horizontal direction; gate structures intersecting the active regions, extending in a second horizontal direction, and including first and second gate structures opposing each other in the second horizontal direction; source/drain regions including first and second source/drain regions, on at least one side of the gate structures and on the active regions; a gate separation pattern between the first and second gate structures; a vertical conductive structure in the gate separation pattern; contact plugs including a first contact plug electrically connected to the first source/drain region and the vertical conductive structure, and a second contact plug electrically connected to the second source/drain region and spaced apart from the vertical conductive structure; and a contact separation pattern separating the first and second contact plugs, having a portion contacting an upper surface of the vertical conductive structure.