公开(公告)号：US20240055493A1

公开(公告)日：2024-02-15

申请号：US18364521

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Kyoungwoo Lee ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a fin-type active pattern, source/drain regions on the fin-type active pattern, an interlayer insulating layer on the isolation insulating layer, and on the source/drain region, a contact structure electrically connected to the source/drain regions, a buried conductive structure electrically connected to the contact structure and buried in the interlayer insulating layer, and a power delivery structure that penetrates the substrate, and is in contact with a bottom surface of the buried conductive structure. The buried conductive structure includes a first contact plug, and a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom surface of the first contact plug. The power delivery structure includes a second contact plug in direct contact with the bottom surface of the first contact plug.

公开(公告)号：US20210082757A1

公开(公告)日：2021-03-18

申请号：US16898906

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US20190244965A1

公开(公告)日：2019-08-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20240047306A1

公开(公告)日：2024-02-08

申请号：US18220971

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongick Anthony LEE ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Sangcheol Last Name not provide

IPC: H01L23/48 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/66545

Abstract: A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

公开(公告)号：US11705454B2

公开(公告)日：2023-07-18

申请号：US17582357

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L29/417 ,  H01L27/02 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/6681 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US10923475B2

公开(公告)日：2021-02-16

申请号：US16391757

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heonjong Shin ,  Sunghun Jung ,  Minchan Gwak ,  Yongsik Jeong ,  Sangwon Jee ,  Sora You ,  Doohyun Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US10861860B2

公开(公告)日：2020-12-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20240395713A1

公开(公告)日：2024-11-28

申请号：US18582859

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Jungho Do ,  Kyoungwoo Lee ,  Gukhee Kim ,  Minchan Gwak

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes first power lines extending on a substrate in a first direction and spaced apart from each other in a second direction, back side power structures on a lower surface of the substrate, standard cells each including an active pattern, a gate pattern intersecting the active pattern, and contacts, power tap cells between at least some of the standard cells and each including vertical power vias, and second power lines electrically connecting at least some of the first power lines to each other. A first portion of the second power lines may extend onto the power tap cells and a second portion of the second power lines that is different from the first portion may extend onto the standard cells. The power tap cells may be arranged in every three or more rows of the standard cells in the second direction in a zigzag pattern.

公开(公告)号：US12014957B2

公开(公告)日：2024-06-18

申请号：US17701275

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmoon Lee ,  Minchan Gwak ,  Heonjong Shin ,  Yongsik Jeong ,  Yeongchang Roh ,  Doohyun Lee ,  Sunghun Jung ,  Sangwon Jee

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/3083 ,  H01L21/32139 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

公开(公告)号：US20240063221A1

公开(公告)日：2024-02-22

申请号：US18125429

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo Lee ,  Yeonho Park ,  Minchan Gwak ,  Hojun Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66439 ,  H01L29/66545

Abstract: A semiconductor device includes active regions, gate structures intersecting the active regions and including gate electrodes, source/drain regions on the active regions on sides of the gate structures, and a gate isolation structure isolating gate structures, which oppose each other, from each other on a region between the active regions. The gate structures that oppose each other include a first gate structure, a second gate structure opposing the first gate structure, a third gate structure extending in parallel to the first gate structure, and a fourth gate structure opposing the third gate structure and extending in parallel to the second gate structure. The gate isolation structure includes a first isolation structure of a line type extending in the first horizontal direction, and second isolation structures of a hole type penetrating through the first isolation structure between the first and second gate structures and between the third and fourth gate structures.