公开(公告)号：US20240395713A1

公开(公告)日：2024-11-28

申请号：US18582859

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Jungho Do ,  Kyoungwoo Lee ,  Gukhee Kim ,  Minchan Gwak

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes first power lines extending on a substrate in a first direction and spaced apart from each other in a second direction, back side power structures on a lower surface of the substrate, standard cells each including an active pattern, a gate pattern intersecting the active pattern, and contacts, power tap cells between at least some of the standard cells and each including vertical power vias, and second power lines electrically connecting at least some of the first power lines to each other. A first portion of the second power lines may extend onto the power tap cells and a second portion of the second power lines that is different from the first portion may extend onto the standard cells. The power tap cells may be arranged in every three or more rows of the standard cells in the second direction in a zigzag pattern.

公开(公告)号：US20240055493A1

公开(公告)日：2024-02-15

申请号：US18364521

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheol Na ,  Kyoungwoo Lee ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a fin-type active pattern, source/drain regions on the fin-type active pattern, an interlayer insulating layer on the isolation insulating layer, and on the source/drain region, a contact structure electrically connected to the source/drain regions, a buried conductive structure electrically connected to the contact structure and buried in the interlayer insulating layer, and a power delivery structure that penetrates the substrate, and is in contact with a bottom surface of the buried conductive structure. The buried conductive structure includes a first contact plug, and a first conductive barrier on a side surface of the first contact plug and spaced apart from a bottom surface of the first contact plug. The power delivery structure includes a second contact plug in direct contact with the bottom surface of the first contact plug.

公开(公告)号：US20240047306A1

公开(公告)日：2024-02-08

申请号：US18220971

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongick Anthony LEE ,  Minchan Gwak ,  Gukhee Kim ,  Youngwoo Kim ,  Sangcheol Last Name not provide

IPC: H01L23/48 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/66545

Abstract: A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

公开(公告)号：US20240282828A1

公开(公告)日：2024-08-22

申请号：US18238872

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  KYOUNGWOO LEE ,  MINCHAN GWAK ,  Gukhee Kim ,  SANGCHEOL NA ,  Anthony Dongick Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An embodiment provides a semiconductor device including a semiconductor substrate having first and second surfaces opposite each other, a channel pattern disposed on the first surface of the semiconductor substrate; source/drain patterns disposed on the first surface of the semiconductor substrate and disposed at both sides of the channel pattern; first and second etch stop films disposed on the first surface of the semiconductor substrate; a contact electrode electrically connected to the source/drain patterns; a lower wire structure disposed on the second surface of the semiconductor substrate; and a through via that passes through the semiconductor substrate, the first etch stop film, and the second etch stop film to connect the contact electrode and the lower wire structure, wherein the through via includes a first portion contacting the contact electrode and a second portion contacting the first portion and disposed between the first portion and the lower wire structure.

公开(公告)号：US20240145556A1

公开(公告)日：2024-05-02

申请号：US18382616

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Hojun Kim ,  Dongick Lee

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.

公开(公告)号：US20240072117A1

公开(公告)日：2024-02-29

申请号：US18307259

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Jeewoong Kim ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Anthony Dongick Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823475 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.