公开(公告)号：US20220406775A1

公开(公告)日：2022-12-22

申请号：US17713834

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

公开(公告)号：US12021146B2

公开(公告)日：2024-06-25

申请号：US17529406

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Wonhyuk Lee ,  Dongkwon Kim ,  Jinwook Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0847

Abstract: Semiconductor devices may include a substrate, an active region that is on the substrate and extends in a first direction, a gate structure that traverses the active region and extends in a second direction that may be different from the first direction, a source/drain region on the active region adjacent a side of the gate structure, an insulating layer on the substrate, the gate structure and the source/drain region, and a contact structure that is in the insulating layer and is connected to the source/drain region. In the source/drain region, a contact region that is in contact with the contact structure includes first and second side regions spaced apart from each other in the second direction and a central region between the first and second side regions, and at least one of the first and second side regions may include a recess.

公开(公告)号：US20250142952A1

公开(公告)日：2025-05-01

申请号：US18796895

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Dongkwon Kim ,  Myeongji Kim ,  Sangduk Park ,  Keunhee Bai ,  Gahyun Lim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L25/18 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of manufacturing an integrated circuit device is provided. The method includes: providing a substrate including a base substrate layer, an insulating substrate layer, and a cover substrate layer that are sequentially stacked in a vertical direction; forming, on the substrate, a stacked structure including a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers that are alternately stacked one layer at a time; and forming a plurality of trench regions to define a plurality of fin-type active regions by etching the stacked structure and the substrate. The he forming of the plurality of trench regions includes, by using the insulating substrate layer as an etch stop layer, etching portions of the stacked structure and the cover substrate layer in the vertical direction up to an upper surface of the insulating substrate layer.

公开(公告)号：US12142607B2

公开(公告)日：2024-11-12

申请号：US17713834

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

公开(公告)号：US20230352547A1

公开(公告)日：2023-11-02

申请号：US18107793

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Sungwoo Kang ,  Dongkwon Kim ,  Hyonwook Ra ,  Jeongyeon Seo ,  Kyungyub Jeon

IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.