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    Method of fabricating a semiconductor memory device including an extension gate cutting region
    5.
    发明授权
    Method of fabricating a semiconductor memory device including an extension gate cutting region 有权

    公开(公告)号：US12218062B2

    公开(公告)日：2025-02-04

    申请号：US18514716

    申请日：2023-11-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim ,  Young-Jin Kwon ,  Geun Won Lim

    IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

    Nonvolatile memory device with h-shaped blocks and method of fabricating the same
    6.
    发明授权
    Nonvolatile memory device with h-shaped blocks and method of fabricating the same 有权

    公开(公告)号：US11594550B2

    公开(公告)日：2023-02-28

    申请号：US16852907

    申请日：2020-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang Min Kim ,  Seung Min Song ,  Jae Hoon Shin ,  Joong Shik Shin ,  Geun Won Lim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11565

    Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

    Semiconductor memory device and method of manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US10797071B2

    公开(公告)日：2020-10-06

    申请号：US16251337

    申请日：2019-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim ,  Kwang Soo Kim ,  Geun Won Lim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L21/28

    Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

    SEMICONDUCTOR MEMORY DEVICES, METHODS FOR FABRICATING THE SAME AND ELECTRONIC SYSTEMS INCLUDING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, METHODS FOR FABRICATING THE SAME AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20250105155A1

    公开(公告)日：2025-03-27

    申请号：US18976693

    申请日：2024-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geun Won Lim ,  Beyoung Hyun Koh ,  Yong Jin Kwon ,  Joong Shik Shin

    IPC: H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

    Semiconductor device including a cell array region and an extension region
    9.
    发明授权
    Semiconductor device including a cell array region and an extension region 有权

    公开(公告)号：US11862566B2

    公开(公告)日：2024-01-02

    申请号：US17018400

    申请日：2020-09-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim ,  Young-Jin Kwon ,  Geun Won Lim

    IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

    Nonvolatile memory device and method of fabricating the same
    10.
    发明授权
    Nonvolatile memory device and method of fabricating the same 有权

    公开(公告)号：US11476275B2

    公开(公告)日：2022-10-18

    申请号：US16998141

    申请日：2020-08-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geun Won Lim

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A nonvolatile memory device and a method of fabricating a nonvolatile memory device, the device including a substrate; a first mold structure on the substrate, the first mold structure including a plurality of first mold insulation films and a plurality of first gate electrodes, which are alternately stacked; a channel structure that penetrates the first mold structure and intersects the plurality of first gate electrodes; and at least one insulation filler that intersects the plurality of first mold insulation films and the plurality of the first gate electrodes, wherein the first mold structure is electrically separated by a word line cutting region extending in a first direction such that the first mold structure includes a first block region and a second block region, and the at least one insulation filler is in the word line cutting region and connects the first block region and the second block region.

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