公开(公告)号：US20240088005A1

公开(公告)日：2024-03-14

申请号：US18297249

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Choongbin Yim ,  Gitae Park

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H10B80/00 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81

Abstract: A semiconductor package includes a first redistribution wiring layer including a first redistribution wiring, a semiconductor chip disposed on the first redistribution wiring layer, a plurality of interposer connectors disposed on the first redistribution wiring layer, each of the plurality of interposer connectors including a first surface facing the first redistribution wiring layer and a second surface opposite the first surface, a plurality of through electrodes and a plurality of core balls formed on the first surface and including a core and a solder layer, the through electrodes being electrically connected to the first redistribution wiring by the core balls, a molding member on the first redistribution wiring layer that covers the semiconductor chip, and a second redistribution wiring layer disposed on the molding member including a second redistribution wiring electrically connected to the through electrodes.

公开(公告)号：US20240128174A1

公开(公告)日：2024-04-18

申请号：US18380424

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Gitae Park ,  Jongbo Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package is provided including: a redistribution substrate having an upper surface and a lower surface, opposite to each other, and including redistribution layers; a semiconductor chip disposed on the upper surface of the redistribution substrate and electrically connected to the redistribution layers; an upper encapsulant encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate; a passive component disposed on the lower surface of the redistribution substrate and electrically connected to the redistribution layer; a lower encapsulant encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings exposing lowermost redistribution layers among the redistribution layers; and a plurality of bumps respectively disposed within the plurality of openings, the bumps respectively including a first portion in contact with the lowermost redistribution layers and a second portion extending from the first portion and protruding partially downwardly of the plurality of openings.

公开(公告)号：US20240047418A1

公开(公告)日：2024-02-08

申请号：US18199553

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Gitae Park ,  Jinwoo Park

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L25/18 ,  H10B80/00 ,  H01L23/49833 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/16 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2224/16227

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution patterns; a sub-semiconductor package including a sub-semiconductor package substrate and a first semiconductor chip that is on the sub-semiconductor package substrate, wherein the sub-semiconductor package substrate is on the redistribution layer and includes a plurality of first lower surface pads; and a second semiconductor chip on the redistribution layer and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the second semiconductor chip includes a chip pad, wherein at least some of the plurality of redistribution patterns of the redistribution layer are overlapped with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively.