公开(公告)号：US20220013464A1

公开(公告)日：2022-01-13

申请号：US17150232

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US20210257305A1

公开(公告)日：2021-08-19

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo SHIM ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US20240128174A1

公开(公告)日：2024-04-18

申请号：US18380424

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Gitae Park ,  Jongbo Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package is provided including: a redistribution substrate having an upper surface and a lower surface, opposite to each other, and including redistribution layers; a semiconductor chip disposed on the upper surface of the redistribution substrate and electrically connected to the redistribution layers; an upper encapsulant encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate; a passive component disposed on the lower surface of the redistribution substrate and electrically connected to the redistribution layer; a lower encapsulant encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings exposing lowermost redistribution layers among the redistribution layers; and a plurality of bumps respectively disposed within the plurality of openings, the bumps respectively including a first portion in contact with the lowermost redistribution layers and a second portion extending from the first portion and protruding partially downwardly of the plurality of openings.

公开(公告)号：US20230075292A1

公开(公告)日：2023-03-09

申请号：US17986169

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US11521934B2

公开(公告)日：2022-12-06

申请号：US17150232

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US10177131B2

公开(公告)日：2019-01-08

申请号：US15442001

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Lyong Kim ,  Jin-woo Park ,  Choongbin Yim ,  Younji Min

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L21/56

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

公开(公告)号：US12148729B2

公开(公告)日：2024-11-19

申请号：US17577653

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

公开(公告)号：US20240079285A1

公开(公告)日：2024-03-07

申请号：US18316682

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongmin Kang ,  Jongbo Shim ,  Ji-Yong Park ,  Choongbin Yim ,  Sungeun Pyo

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate, a first semiconductor chip on the first substrate, a molding layer on the first substrate and the first semiconductor chip and has a plurality of recesses, a plurality of substrate connection terminals on the first substrate and in the plurality of recesses, and a second semiconductor chip on the plurality of substrate connection terminals. The plurality of recesses and the plurality of substrate connection terminals are horizontally spaced apart from the first semiconductor chip. The molding layer is spaced apart from the second semiconductor chip.

公开(公告)号：US20240063181A1

公开(公告)日：2024-02-22

申请号：US18124183

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jiyong Park ,  Jongbo Shim ,  Choongbin Yim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H10B80/00 ,  H01L25/0655 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/08112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32227 ,  H01L2224/48228 ,  H01L2924/1436 ,  H01L2924/1431

Abstract: A semiconductor package may include a package substrate having a first surface and a second surface vertically opposite to each other, a first mounting region and a second mounting region horizontally spaced apart from each other, and first and second semiconductor devices respectively mounted on the first and second mounting regions on the first surface of the package substrate. The package substrate may include wiring patterns electrically connected to the first and second semiconductor devices, dummy patterns electrically insulated from the first and second semiconductor devices, and a reinforcing structure that extends along perimeters of the first and second mounting regions on the first surface of the package substrate, and is bonded to at least portions of the dummy patterns.

公开(公告)号：US11710673B2

公开(公告)日：2023-07-25

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Dongwook Kim ,  Hyunki Kim ,  Jongbo Shim ,  Jihwang Kim ,  Sungkyu Park ,  Yongkwan Lee ,  Byoungwook Jang

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/12 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.