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    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME
    3.
    发明申请
    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220116198A1

    公开(公告)日：2022-04-14

    申请号：US17336625

    申请日：2021-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul NA ,  Sumin KIM ,  Hongrak SON ,  Junho SHIN

    IPC: H04L9/00 ,  H04L9/30

    Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive ciphertext data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the ciphertext data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the ciphertext data.

    MEMORY CONTROLLER FOR PERFORMING EFFICIENT ERROR CORRECTION CODE (ECC) DECODING AND A STORAGE DEVICE INCLUDING THE SAME
    4.
    发明申请
    MEMORY CONTROLLER FOR PERFORMING EFFICIENT ERROR CORRECTION CODE (ECC) DECODING AND A STORAGE DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250021431A1

    公开(公告)日：2025-01-16

    申请号：US18635073

    申请日：2024-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junho SHIN ,  Hanbyeul NA ,  Jaehun JANG ,  Mankeun SEO ,  Dongmin SHIN

    IPC: G06F11/10

    Abstract: A memory controller including: a data formatter receiving first to N-th hard decision data and first to N-th soft decision data, and performing a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data; and an error correction code (ECC) circuit receiving the first to N-th hard decision data and the first to N-th soft decision data from the data formatter and correcting an error on the first page by ECC decoding processing, wherein the data formatter performs the formatting operation such that the first to N-th hard decision data and the first to N-th soft decision data are provided to the ECC circuit in an order different from an order of the first to N-th hard decision data and the first to N-th soft decision data were received from the memory device.

    STORAGE CONTROLLER, STORAGE SYSTEM AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    STORAGE CONTROLLER, STORAGE SYSTEM AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220365847A1

    公开(公告)日：2022-11-17

    申请号：US17816554

    申请日：2022-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul NA ,  Jaehun Jang ,  Hongrak Son

    IPC: G06F11/10 ,  G06F11/07

    Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

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