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    MEMORY CONTROLLER FOR PERFORMING EFFICIENT ERROR CORRECTION CODE (ECC) DECODING AND A STORAGE DEVICE INCLUDING THE SAME
    1.
    发明申请
    MEMORY CONTROLLER FOR PERFORMING EFFICIENT ERROR CORRECTION CODE (ECC) DECODING AND A STORAGE DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250021431A1

    公开(公告)日：2025-01-16

    申请号：US18635073

    申请日：2024-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junho SHIN ,  Hanbyeul NA ,  Jaehun JANG ,  Mankeun SEO ,  Dongmin SHIN

    IPC: G06F11/10

    Abstract: A memory controller including: a data formatter receiving first to N-th hard decision data and first to N-th soft decision data, and performing a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data; and an error correction code (ECC) circuit receiving the first to N-th hard decision data and the first to N-th soft decision data from the data formatter and correcting an error on the first page by ECC decoding processing, wherein the data formatter performs the formatting operation such that the first to N-th hard decision data and the first to N-th soft decision data are provided to the ECC circuit in an order different from an order of the first to N-th hard decision data and the first to N-th soft decision data were received from the memory device.

    METHOD OF MANAGING SEMICONDUCTOR PROCESSING APPARATUS
    3.
    发明公开
    METHOD OF MANAGING SEMICONDUCTOR PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20240272561A1

    公开(公告)日：2024-08-15

    申请号：US18373030

    申请日：2023-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junho SHIN ,  Seungbeom PARK ,  Jangwoon SUNG ,  Hojun LEE ,  Wookrae KIM ,  Myungjun LEE

    IPC: G03F7/00 ,  G06T7/00

    CPC classification number: G03F7/706839 ,  G03F7/706 ,  G03F7/70641 ,  G06T7/001 ,  G06T2207/30148

    Abstract: Provided is a method of managing a semiconductor processing apparatus, including irradiating, by a light source, a plurality of regions included in a diffuser on a mask stage with extreme ultraviolet (EUV) light, reflecting or transmitting, by the diffuser, the EUV light, transmitting, by an optical system, the EUV light from the diffuser, receiving, by an image sensor, the EUV light from the optical system, obtaining, by the image sensor, a plurality of original images corresponding to the plurality of regions, generating, based on an optical prediction model, a plurality of predictive images estimating a diffraction pattern in the image sensor, adjusting an optical prediction model by comparing the plurality of predictive images with the plurality of original images, and generating, based on the optical prediction model, a plurality of wavefront images corresponding to optical characteristics of each of the plurality of mirrors.

    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME
    5.
    发明申请
    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220116198A1

    公开(公告)日：2022-04-14

    申请号：US17336625

    申请日：2021-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul NA ,  Sumin KIM ,  Hongrak SON ,  Junho SHIN

    IPC: H04L9/00 ,  H04L9/30

    Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive ciphertext data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the ciphertext data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the ciphertext data.

    RESISTIVE MEMORY DEVICES AND METHODS OF OPERATING RESISTIVE MEMORY DEVICES
    6.
    发明申请
    RESISTIVE MEMORY DEVICES AND METHODS OF OPERATING RESISTIVE MEMORY DEVICES 有权

    公开(公告)号：US20210020236A1

    公开(公告)日：2021-01-21

    申请号：US16745823

    申请日：2020-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin BAEK ,  Jinyoung KIM ,  Junho SHIN

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.

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