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    HOMOMORPHIC ENCRYPTION PROCESSING DEVICE, SYSTEM INCLUDING THE SAME AND METHOD OF PERFORMING HOMOMORPHIC ENCRYPTION PROCESSING
    1.
    发明申请
    HOMOMORPHIC ENCRYPTION PROCESSING DEVICE, SYSTEM INCLUDING THE SAME AND METHOD OF PERFORMING HOMOMORPHIC ENCRYPTION PROCESSING 有权

    公开(公告)号：US20210344479A1

    公开(公告)日：2021-11-04

    申请号：US17115161

    申请日：2020-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wijik LEE ,  Youngsik MOON ,  Hongrak SON ,  Jaehun JANG

    IPC: H04L9/00 ,  H04L9/14 ,  H04L9/30

    Abstract: A homomorphic encryption processing device includes the processing circuitry is configured to generate ciphertext operation level information based on field information. The field information represents a technology field to which homomorphic encryption processing is applied. The ciphertext operation level information represents a maximum number of multiplication operations between homomorphic ciphertexts without a bootstrapping process. The processing circuitry is further configured to select and output a homomorphic encryption parameter based on the ciphertext operation level information. The processing circuitry is further configured to perform one of a homomorphic encryption, a homomorphic decryption and a homomorphic operation, based on the homomorphic encryption parameter. The homomorphic encryption processing device may adaptively generate a homomorphic encryption parameter according to a ciphertext operation level information determined based on a field information, and may perform a homomorphic encryption, a homomorphic decryption and a homomorphic operation based on the homomorphic encryption parameter.

    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME
    2.
    发明申请
    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210160109A1

    公开(公告)日：2021-05-27

    申请号：US16911801

    申请日：2020-06-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hongrak SON ,  Geunyeong YU ,  Pilsang YOON ,  Jaehun JANG

    IPC: H04L27/04 ,  H04L27/06 ,  H04L1/00

    Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME
    4.
    发明申请
    HOMOMORPHIC OPERATION ACCELERATOR AND HOMOMORPHIC OPERATION PERFORMING DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220116198A1

    公开(公告)日：2022-04-14

    申请号：US17336625

    申请日：2021-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanbyeul NA ,  Sumin KIM ,  Hongrak SON ,  Junho SHIN

    IPC: H04L9/00 ,  H04L9/30

    Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive ciphertext data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the ciphertext data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the ciphertext data.

    MEMORY CONTROLLER CALCULATING OPTIMAL READ LEVEL, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY CONTROLLER
    5.
    发明申请
    MEMORY CONTROLLER CALCULATING OPTIMAL READ LEVEL, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY CONTROLLER 有权

    公开(公告)号：US20230057932A1

    公开(公告)日：2023-02-23

    申请号：US17685024

    申请日：2022-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwanwoo NOH ,  Hyeonjong SONG ,  Wijik LEE ,  Hongrak SON ,  Dongmin SHIN ,  Seonghyeog CHOI

    IPC: G06F3/06

    Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

    MEMORY DEVICE STORING PARITY AND MEMORY SYSTEM INCLUDING THE SAME
    6.
    发明申请
    MEMORY DEVICE STORING PARITY AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220130485A1

    公开(公告)日：2022-04-28

    申请号：US17244195

    申请日：2021-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun HWANG ,  Heeyoul KWAK ,  Bohwan JUN ,  Hongrak SON ,  Dongmin SHIN ,  Geunyeong YU

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

    Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.

    ERROR CHECK CODE (ECC) DECODER AND MEMORY SYSTEM INCLUDING ECC DECODER
    7.
    发明申请
    ERROR CHECK CODE (ECC) DECODER AND MEMORY SYSTEM INCLUDING ECC DECODER 有权

    公开(公告)号：US20210397514A1

    公开(公告)日：2021-12-23

    申请号：US17134961

    申请日：2020-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun HWANG ,  Hongrak SON ,  Dongmin SHIN

    IPC: G06F11/10 ,  H03M13/11 ,  H03M13/45

    Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.

    GENERALIZED LDPC ENCODER, GENERALIZED LDPC ENCODING METHOD AND STORAGE DEVICE
    8.
    发明公开
    GENERALIZED LDPC ENCODER, GENERALIZED LDPC ENCODING METHOD AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20240120945A1

    公开(公告)日：2024-04-11

    申请号：US18225313

    申请日：2023-07-24

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： Daeyeol YANG ,  Bohwan JUN ,  Hongrak SON ,  Geunyeong YU ,  Youngjun HWANG

    IPC: H03M13/11

    CPC classification number: H03M13/116 ,  H03M13/1108 ,  H03M13/1177

    Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

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