公开(公告)号：US20170047243A1

公开(公告)日：2017-02-16

申请号：US15335743

申请日：2016-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong SHIN ,  Sungmin Kim ,  Byungseo Kim ,  Sunhom Steve Paak ,  Hyunjun Bae

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/76202 ,  H01L21/265 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 本发明构思的半导体器件可以包括散热片区域，其包括通过设置在其间的隔离绝缘层彼此分离和隔离的第一鳍片区域和第二鳍片区域，与第一鳍片区域交叉的第一栅极，与第二鳍片相交的第二栅极 翅片子区域和与隔离绝缘层相交的第三栅极。

公开(公告)号：US20180130796A1

公开(公告)日：2018-05-10

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan JUN ,  Deokhan BAE ,  HeonJong SHIN ,  Jaeran JANG ,  Moon Gi CHO ,  YoungWoo CHO

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US20210013206A1

公开(公告)日：2021-01-14

申请号：US17038435

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong SHIN ,  Sunghun JUNG ,  Minchan GWAK ,  Yongsik JEONG ,  Sangwon JEE ,  Sora YOU ,  Doohyun LEE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/417

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

公开(公告)号：US20190148216A1

公开(公告)日：2019-05-16

申请号：US16243464

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： HeonJong SHIN ,  Sungmin KIM ,  Byungseo KIM ,  Sunhom Steve PAAK ,  Hyunju BAE

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L29/78 ,  H01L27/088

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.