公开(公告)号：US20240267138A1

公开(公告)日：2024-08-08

申请号：US18431087

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yungeun NAM ,  Hobin SONG ,  Hyogyuem RHEW ,  Jaehyun PARK ,  Jongshin SHIN

IPC: H04B17/29 ,  H04B17/19

CPC classification number: H04B17/297 ,  H04B17/19 ,  H04B17/295

Abstract: A transceiver according to an aspect of the inventive concepts may include a transmitter, a first receiver pad configured to receive a first external voltage, a second receiver pad configured to receive a second external voltage, a receiver configured to generate a test target signal based on the first external voltage and the second external voltage, and a digital logic configured to perform a loopback test on a reception path of a data signal by transmitting the data signal and receiving the test target signal.

公开(公告)号：US20230130236A1

公开(公告)日：2023-04-27

申请号：US17972869

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hobin SONG ,  Yungeun NAM ,  Byeonggyu PARK ,  Jaehyun PARK ,  Hajung PARK ,  Junhan BAE

IPC: H04B1/18 ,  H04B17/21

Abstract: A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.

公开(公告)号：US20230099986A1

公开(公告)日：2023-03-30

申请号：US17943551

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyun LEE ,  Hanseok KIM ,  Jiyoung KIM ,  Jaehyun PARK ,  Hyeonju LEE ,  Kangjik KIM ,  Sunggeun KIM ,  Seuk SON ,  Hobin SONG ,  Nakwon LEE

IPC: G01R25/04 ,  H03L7/08 ,  H03L7/085

Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.

公开(公告)号：US20240302432A1

公开(公告)日：2024-09-12

申请号：US18597499

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hobin SONG ,  Juyun Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Sooeun Lee ,  Insik Hwang

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3187 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

CPC classification number: G01R31/318328 ,  G01R31/31724 ,  G01R31/3187 ,  H03K5/13 ,  H03L7/0807 ,  H03K2005/00052 ,  H03L7/0812

Abstract: A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

公开(公告)号：US20220209930A1

公开(公告)日：2022-06-30

申请号：US17469062

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanseok KIM ,  Hobin SONG ,  Jaehyun PARK

IPC: H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/093

Abstract: A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.

公开(公告)号：US20220200605A1

公开(公告)日：2022-06-23

申请号：US17503802

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsuk JANG ,  Hanseok KIM ,  Jaehyun PARK ,  Hobin SONG ,  Jongshin SHIN ,  Youngjin CHUNG

IPC: H03L7/08 ,  H03L7/081 ,  H04L1/20 ,  H04L1/00

Abstract: An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.