公开(公告)号：US20240292634A1

公开(公告)日：2024-08-29

申请号：US18499446

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myunghun LEE ,  Homoon SHIN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device may include a first structure and a second structure bonded to the first structure. The first structure may have a plurality of planes and a pad part between two planes adjacent to each other among the plurality of planes. Each of the plurality of planes may include a memory cell. The second structure may include a peripheral circuit. The plurality of planes may be minimum units in which operations are independently performed and may be in an n×m array (n and m being integers of 2 or larger). The pad part may be between the rows and/or between the columns of the n×m array.

公开(公告)号：US20220392532A1

公开(公告)日：2022-12-08

申请号：US17578840

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ansoo PARK ,  Ahreum KIM ,  Homoon SHIN

IPC: G11C16/08 ,  G11C16/30

Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.

公开(公告)号：US20240224522A1

公开(公告)日：2024-07-04

申请号：US18475070

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Homoon SHIN ,  Jonghoon PARK ,  Juyoung YANG ,  Jungseok HWANG ,  Sunghoon KIM ,  Pansuk KWAK ,  Ahreum KIM ,  Myunghun LEE ,  Changyeon YU ,  Mookyu BAE ,  Sungun LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A non-volatile memory device may include a memory cell region and a peripheral circuit region positioned below the memory cell region in the vertical direction. The memory cell region may include a plurality of channel structures extending in a vertical direction, a first metal layer over the plurality of channel structures, a first capping layer over the first metal layer, a first upper insulation layer over the first capping layer, and at least one first dummy contact penetrating through the first capping layer. The first metal layer may include a plurality of bit lines and at least one dummy bit line. The bit lines may be respectively connected to the plurality of channel structures. The at least one first dummy contact may be on the at least one dummy bit line and may provide a migration path for hydrogen ions in the first upper insulation layer.