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    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE
    4.
    发明公开
    METHOD OF CONTROLLING ROW HAMMER AND A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240233801A1

    公开(公告)日：2024-07-11

    申请号：US18610420

    申请日：2024-03-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin YOU ,  Wonhyung SONG ,  Hoyoun KIM

    IPC: G11C11/406 ,  G11C11/4093 ,  G11C11/4096

    CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220139482A1

    公开(公告)日：2022-05-05

    申请号：US17326416

    申请日：2021-05-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Hoyoun KIM ,  Suhun LIM ,  Sunghye CHO

    IPC: G11C29/42 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

    MEMORY CONTROLLERS, MEMORY SYSTEMS AND MEMORY MODULES
    6.
    发明申请
    MEMORY CONTROLLERS, MEMORY SYSTEMS AND MEMORY MODULES 有权

    公开(公告)号：US20210357287A1

    公开(公告)日：2021-11-18

    申请号：US17132028

    申请日：2020-12-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoyoun KIM ,  Kijun LEE ,  Chanki KIM ,  Myungkyu LEE

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

    Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

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