公开(公告)号：US20240201868A1

公开(公告)日：2024-06-20

申请号：US18588599

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20210191809A1

公开(公告)日：2021-06-24

申请号：US16909730

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol SONG ,  Sungrae KIM ,  Kijun LEE

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

公开(公告)号：US20230344444A1

公开(公告)日：2023-10-26

申请号：US17975034

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu SEOL ,  Sungrae KIM ,  Chisung OH ,  Junghwan CHOI

IPC: H03M5/14 ,  H04L1/00

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

公开(公告)号：US20230146904A1

公开(公告)日：2023-05-11

申请号：US17984430

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu LEE ,  Kijun LEE ,  Sunghye CHO ,  Sungrae KIM

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/159 ,  H03M13/611

Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20220139482A1

公开(公告)日：2022-05-05

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Hoyoun KIM ,  Suhun LIM ,  Sunghye CHO

IPC: G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.