公开(公告)号：US20240349490A1

公开(公告)日：2024-10-17

申请号：US18501980

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huije RYU ,  Hyungki CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor memory device includes a bit line that extends in a first direction, semiconductor patterns disposed on the bit line and spaced apart from each other in the first direction and each including a first vertical part, a second vertical part, and a horizontal part, first and second word lines disposed on the horizontal part and respectively adjacent to the first and second vertical parts, and a semiconductor dielectric pattern disposed on the bit line and between the semiconductor patterns. The semiconductor dielectric pattern includes a lower capping pattern, sidewall dielectric patterns spaced apart from each other in the first direction on the lower capping pattern, an air gap between the sidewall dielectric patterns, and an upper capping pattern disposed on the sidewall dielectric patterns. Top surfaces of the sidewall dielectric patterns are at the same height as top surfaces of the first and second vertical parts.

公开(公告)号：US20250126886A1

公开(公告)日：2025-04-17

申请号：US18917227

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Minsu SEOL ,  Junyoung KWON ,  Huije RYU

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786

Abstract: Provided is a semiconductor device including a two-dimensional (2D) material. The semiconductor device may include a first channel including a first 2D material layer, a second channel apart from the first channel in a first direction and including a second 2D material layer, a common gate electrode between the first channel and the second channel, a first electrode and a second electrode apart from each other and respectively in contact with the first channel and the second channel, and a common electrode apart from the first electrode and the second electrode in a second direction intersecting the first direction and in contact with the first channel and the second channel. One of the first channel and the second channel may be an n-type channel and the other one may be a p-type channel.

公开(公告)号：US20250107096A1

公开(公告)日：2025-03-27

申请号：US18581186

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Junyoung KWON ,  Huije RYU ,  Minsu SEOL

IPC: H10B43/30 ,  H10B43/27

Abstract: A memory device may include a gate electrode, a channel layer spaced apart from the gate electrode, a charge trap layer between the gate electrode and the channel layer, and a two-dimensional material layer arranged between the charge trap layer and the gate electrode. The two-dimensional material layer may include a material having an electron affinity of less than 1 eV.

公开(公告)号：US20250098390A1

公开(公告)日：2025-03-20

申请号：US18653130

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonseok KIM ,  Joonyun KIM ,  Huije RYU ,  Chang Seok LEE ,  Luhing HU

IPC: H01L27/15 ,  H01L25/075 ,  H01L25/16 ,  H01L27/12 ,  H01L33/62

Abstract: A panel includes: a substrate, unit pixels arranged repeatedly on the substrate, and unit pixel circuits including a unit pixel circuit repeatedly arranged on the substrate and electrically connected to a unit pixel. Each unit pixel includes a red sub-pixel including a red optoelectronic element configured to display red color or detect red light, a green sub-pixel including a green optoelectronic element configured to display green color or detect green light, and a blue sub-pixel including a blue optoelectronic element configured to display blue color or detect blue light. Each unit pixel circuit includes a red pixel circuit electrically connected to the red optoelectronic element, a green pixel circuit electrically connected to the green optoelectronic element, and a blue pixel circuit electrically connected to the blue optoelectronic element. The red pixel circuit, the green pixel circuit, and the blue pixel circuit are stacked along a thickness direction of the substrate.

公开(公告)号：US20230307551A1

公开(公告)日：2023-09-28

申请号：US18092973

申请日：2023-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwon YOO ,  Yongseok KIM ,  Min Tae RYU ,  Huije RYU ,  Yongjin LEE ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L29/786 ,  H10B12/00 ,  H01L27/146 ,  H01L29/417

CPC classification number: H01L29/78693 ,  H01L27/10814 ,  H01L27/14616 ,  H01L29/41733 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.