公开(公告)号：US20220321112A1

公开(公告)日：2022-10-06

申请号：US17842881

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: H03K5/156 ,  H03L7/081 ,  G11C8/18 ,  G11C7/22 ,  G11C8/10

Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

公开(公告)号：US20210335403A1

公开(公告)日：2021-10-28

申请号：US17109567

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: G11C7/22 ,  G11C8/10 ,  G11C7/10 ,  H03L7/081 ,  H03L7/085

Abstract: A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

公开(公告)号：US20220392503A1

公开(公告)日：2022-12-08

申请号：US17567306

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun CHANG ,  Hundae CHOI

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02 ,  G11C8/18

Abstract: A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

公开(公告)号：US20210006254A1

公开(公告)日：2021-01-07

申请号：US16800038

申请日：2020-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwapyong KIM ,  Hundae CHOI

IPC: H03L7/081 ,  G11C7/22 ,  G11C8/18 ,  G11C8/10 ,  G11C7/10 ,  H03L7/085 ,  H03L7/18

Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

公开(公告)号：US20220084616A1

公开(公告)日：2022-03-17

申请号：US17225548

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae CHOI

IPC: G11C29/12 ,  G11C29/46 ,  G11C29/36 ,  H03L7/081 ,  H03L7/083 ,  H03L7/08

Abstract: A clock locking method of a memory device, may include performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized, monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.

公开(公告)号：US20220006461A1

公开(公告)日：2022-01-06

申请号：US17149039

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: H03L7/081 ,  G11C11/4076

Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.