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    Semiconductor device and method of forming the same
    2.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09240415B2

    公开(公告)日：2016-01-19

    申请号：US14312777

    申请日：2014-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

    IPC: H01L21/70 ,  H01L27/108 ,  H01L29/06 ,  H01L21/265 ,  H01L21/28

    CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

    Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

    Abstract translation: 提供半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

    Semiconductor integrated circuit devices including gates having connection lines thereon
    3.
    发明授权
    Semiconductor integrated circuit devices including gates having connection lines thereon 有权
    包括其上具有连接线的门的半导体集成电路器件

    公开(公告)号：US09299827B2

    公开(公告)日：2016-03-29

    申请号：US14516201

    申请日：2014-10-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bong-Soo Kim ,  Soo-Ho Shin ,  Ho-In Ryu ,  Hyeong-Sun Hong

    IPC: H01L27/108 ,  H01L29/78 ,  H01L27/02

    CPC classification number: H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

    Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

    Abstract translation: 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

    MOS transistors including U shaped channels regions with separated protruding portions
    4.
    发明授权
    MOS transistors including U shaped channels regions with separated protruding portions 有权
    MOS晶体管包括具有分离的突出部分的U形沟道区域

    公开(公告)号：US08957474B2

    公开(公告)日：2015-02-17

    申请号：US13894575

    申请日：2013-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Ik Kim ,  Ji-Young Kim ,  Hyeong-Sun Hong

    IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/108 ,  H01L29/423

    CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/0203 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

    Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.

    Abstract translation: MOS晶体管可以包括U形横截面沟道区域，其包括由沟槽分隔开的间隔开的突出部分，并且通过沟道区域的连接部分在通道区域的间隔开的突出部分的下端处彼此连接 。 第一和第二杂质区域可以位于形状的横截面沟道区域的相对端并且通过沟槽彼此分离。 栅电极可以覆盖包括间隔开的突出部分和连接部分的u形横截面沟道区域的至少一个平面，并暴露第一和第二杂质区域。

    MOS TRANSISTORS INCLUDING U SHAPED CHANNELS REGIONS WITH SEPARATED PROTRUDING PORTIONS
    5.
    发明申请
    MOS TRANSISTORS INCLUDING U SHAPED CHANNELS REGIONS WITH SEPARATED PROTRUDING PORTIONS 有权
    包含U形通道的MOS晶体管，具有独立的输入部分

    公开(公告)号：US20130307068A1

    公开(公告)日：2013-11-21

    申请号：US13894575

    申请日：2013-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Ik Kim ,  Ji-Young Kim ,  Hyeong-Sun Hong

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/0203 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

    Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.

    Abstract translation: MOS晶体管可以包括U形横截面沟道区域，其包括由沟槽分隔开的间隔开的突出部分，并且通过沟道区域的连接部分在通道区域的间隔开的突出部分的下端处彼此连接 。 第一和第二杂质区域可以位于形状的横截面沟道区域的相对端并且通过沟槽彼此分离。 栅电极可以覆盖包括间隔开的突出部分和连接部分的u形横截面沟道区域的至少一个平面，并暴露第一和第二杂质区域。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20150008530A1

    公开(公告)日：2015-01-08

    申请号：US14312777

    申请日：2014-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/06 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

    Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

    Abstract translation: 提供一种半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

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