公开(公告)号：US10332831B2

公开(公告)日：2019-06-25

申请号：US15638552

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

公开(公告)号：US09960039B2

公开(公告)日：2018-05-01

申请号：US15291780

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Eun-Jung Kim ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.

公开(公告)号：US20160049460A1

公开(公告)日：2016-02-18

申请号：US14636397

申请日：2015-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

IPC: H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的接触焊盘并穿透层间绝缘层，层间绝缘层上的停止绝缘层，接触焊盘上的存储电极，上部部分之间的上部支撑 存储电极，存储电极和上支撑体之间的侧支撑体，存储电极上的电容器电介质层，侧支撑体和上支撑件，以及电容器介电层上的平板电极。

公开(公告)号：US09601494B2

公开(公告)日：2017-03-21

申请号：US14636397

申请日：2015-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

公开(公告)号：US08957474B2

公开(公告)日：2015-02-17

申请号：US13894575

申请日：2013-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Ik Kim ,  Ji-Young Kim ,  Hyeong-Sun Hong

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/0203 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.

Abstract translation: MOS晶体管可以包括U形横截面沟道区域，其包括由沟槽分隔开的间隔开的突出部分，并且通过沟道区域的连接部分在通道区域的间隔开的突出部分的下端处彼此连接 。 第一和第二杂质区域可以位于形状的横截面沟道区域的相对端并且通过沟槽彼此分离。 栅电极可以覆盖包括间隔开的突出部分和连接部分的u形横截面沟道区域的至少一个平面，并暴露第一和第二杂质区域。

公开(公告)号：US08878299B2

公开(公告)日：2014-11-04

申请号：US13770573

申请日：2013-02-19

Applicant: Samsung Electronics Co. Ltd.

Inventor： Ki-Seok Lee ,  Dae-Ik Kim

IPC: H01L21/70 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L29/785

Abstract: A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed.

Abstract translation: 半导体器件可以包括多个存储单元。 存储单元可以形成有各自的翅片形状的有源区域，其中形成有相应的凹部。 散热片的厚度可以围绕凹部相对较厚，例如通过围绕凹部的选择性外延生长。 附加厚度可以是不对称的，使得一侧的翅片的部分大于相对侧。 还公开了相关方法和系统。

公开(公告)号：US20130307068A1

公开(公告)日：2013-11-21

申请号：US13894575

申请日：2013-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Ik Kim ,  Ji-Young Kim ,  Hyeong-Sun Hong

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/0203 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.

Abstract translation: MOS晶体管可以包括U形横截面沟道区域，其包括由沟槽分隔开的间隔开的突出部分，并且通过沟道区域的连接部分在通道区域的间隔开的突出部分的下端处彼此连接 。 第一和第二杂质区域可以位于形状的横截面沟道区域的相对端并且通过沟槽彼此分离。 栅电极可以覆盖包括间隔开的突出部分和连接部分的u形横截面沟道区域的至少一个平面，并暴露第一和第二杂质区域。

公开(公告)号：US20170025420A1

公开(公告)日：2017-01-26

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。

公开(公告)号：US20160020213A1

公开(公告)日：2016-01-21

申请号：US14692789

申请日：2015-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。

公开(公告)号：US09159730B2

公开(公告)日：2015-10-13

申请号：US14097786

申请日：2013-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Ho-In Ryu ,  Nak-Jin Son ,  Yoo-Sang Hwang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。