公开(公告)号：US20230116461A1

公开(公告)日：2023-04-13

申请号：US17876109

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchul PARK ,  Hyonwook RA

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes a first gate electrode and a second gate electrode which are each on a substrate and extend in a first direction, first and second source/drain patterns spaced apart from the first and second gate electrodes in a second direction which crosses the first direction, and an active contact in common connection with top surfaces of the first source/drain pattern and the second source/drain pattern. The active contact comprises a first portion on the first source/drain pattern and a second portion on the second source/drain pattern. The device includes an insulating separation pattern which extends in the second direction to separate the first gate electrode from the second gate electrode, and the active contact comprises a third portion which extends to a region below a bottom surface of the insulating separation pattern to connect the first and second portions of the active contact to each other.

公开(公告)号：US20240347424A1

公开(公告)日：2024-10-17

申请号：US18531235

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik SHIN ,  Kyongbeom KOH ,  Eunkyung KO ,  Hyonwook RA ,  Dongsoo SEO ,  Jeongyeon SEO ,  Kwangyong YANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device may include an active region extending in a first direction; a gate structure extending in a second direction on the active region; a source/drain region on the active region and disposed at least one side of the gate structure; a contact structure on the source/drain region; a device isolation layer surrounding the active region; an interlayer insulating layer on the device isolation layer, the gate structure, and the source/drain region; a vertical power structure penetrating through the device isolation and interlayer insulating layers and connected to the contact structure; a rear power structure electrically connected to the vertical power structure and surrounding an entirety of a lower surface and a portion of a side surface of the vertical power structure; a vertical insulating film between the vertical power structure and the rear power structure; and a rear insulating film covering a side of the rear power structure.

公开(公告)号：US20190148384A1

公开(公告)日：2019-05-16

申请号：US15983405

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan BAE ,  Hyonwook RA ,  Hyung Jong LEE ,  Juhun PARK

IPC: H01L27/11 ,  G11C11/412 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.