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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150132943A1

    公开(公告)日：2015-05-14

    申请号：US14539558

    申请日：2014-11-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Yoo-sang HWANG

    IPC: H01L21/768 ,  H01L27/105 ,  H01L21/311

    CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成隔离的接触填充部分和蚀刻控制部分，隔离的接触填充部分填充限定在支撑层中的接触孔，并且在垂直于第一方向的第一方向和第二方向彼此间隔开，并且蚀刻 围绕隔离的接触填充部分的控制层，在隔离的接触填充部分和蚀刻控制部分上形成互连层，以及通过光刻蚀互连层，隔离接触图案和蚀刻控制部分形成互连图案， 图案在第一方向上相对较窄并且在第二方向上相对较宽。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150380508A1

    公开(公告)日：2015-12-31

    申请号：US14697782

    申请日：2015-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Sung-eui KIM

    IPC: H01L29/45 ,  H01L23/528

    CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

    Abstract translation: 半导体器件包括：半导体衬底，包括多个有效区域，与多个有源区域交叉的位线;将多个有源区域的第一有源区域与位线连接的直接接触;覆盖侧壁 并且在比半导体衬底的上表面的电平低的水平处延伸的触点焊盘与多个有源区域的与第一有源区域相邻的第二有源区域的侧壁连接的接触焊盘， 第一绝缘图案限定了暴露绝缘间隔件和接触焊盘的接触孔，以及与接触垫连接并填充接触孔的埋入触头。

    SEMICONDUCTOR DEVICE INCLUDING LANDING PAD
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING LANDING PAD 审中-公开
    半导体器件，包括着陆垫

    公开(公告)号：US20150214146A1

    公开(公告)日：2015-07-30

    申请号：US14591732

    申请日：2015-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Sung-eui KIM ,  Hoon JEONG

    IPC: H01L23/528

    CPC classification number: H01L27/10885 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.

    Abstract translation: 一种半导体器件包括：衬底，包括有源区，与衬底分离的多个导线结构;多个导线结构之间的多个接触插塞;多个接地焊盘，其连接到多个 接触插塞，多个着陆焊盘之间的着陆焊盘绝缘图案，以及在多个导线结构之间的着陆焊盘绝缘图案和第一导线结构之间的第一绝缘隔离件。

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