公开(公告)号：US20230229073A1

公开(公告)日：2023-07-20

申请号：US18048205

申请日：2022-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan KIM ,  Jichang SIM ,  Jongmin LEE ,  Sangeun GO ,  Ohhun KWON ,  Hyuckjoon KWON

IPC: G03F1/36 ,  G03F1/70

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.

公开(公告)号：US20240202424A1

公开(公告)日：2024-06-20

申请号：US18335428

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichang SIM ,  Ohhun KWON ,  Hyuckjoon KWON ,  Bok-Yeon WON

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.

公开(公告)号：US20140306293A1

公开(公告)日：2014-10-16

申请号：US14186134

申请日：2014-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hum BAEK ,  Hyuckjoon KWON

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0921

Abstract: The semiconductor memory device including a first sense amplifier region including first metal-oxide-semiconductor (MOS) transistors disposed in a well on a semiconductor substrate, a second sense amplifier region adjacent to the well and including second MOS transistors disposed on the semiconductor substrate, a guard band having a bar type structure and provided between the first MOS transistors in the well, and a guard ring partially or fully enclosing the second sense amplifier region in the semiconductor substrate may be provided.

Abstract translation: 该半导体存储器件包括：第一读出放大器区域，包括设置在半导体衬底上的阱中的第一金属氧化物半导体（MOS）晶体管;与该阱相邻的第二读出放大器区域，并且包括设置在半导体衬底上的第二MOS晶体管; 可以提供具有条形结构并设置在阱中的第一MOS晶体管之间的保护带和部分或全部包围半导体衬底中的第二读出放大器区的保护环。