公开(公告)号：US11995417B2

公开(公告)日：2024-05-28

申请号：US18342385

申请日：2023-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Nam Hwang ,  Hyung-Dal Kwon ,  Dae Hyun Kim

IPC: G06F7/544 ,  G06F17/15 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06F17/15 ,  G06N3/045 ,  G06N3/063

Abstract: Provided is a neural processing unit that performs application-work including a first neural network operation, the neural processing unit includes a first processing core configured to execute the first neural network operation, a hardware block reconfigurable as a hardware core configured to perform hardware block-work, and at least one processor configured to execute computer-readable instructions to distribute a part of the application-work as the hardware block-work to the hardware block based on a first workload of the first processing core.

公开(公告)号：US11790232B2

公开(公告)日：2023-10-17

申请号：US18095674

申请日：2023-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal Kwon

IPC: G06N3/08 ,  G06N3/04 ,  H03M7/30

CPC classification number: G06N3/08 ,  G06N3/04 ,  H03M7/30

Abstract: A neural network deep learning data control apparatus includes: a memory; an encoding circuit configured to receive a data sequence, generate a compressed data sequence in which consecutive invalid bits in a bit string of the data sequence are compressed into a single bit of the compressed data sequence, generate a validity determination sequence indicating a valid bit and an invalid bit in a bit string of the compressed data sequence, and write the compressed data sequence and the validity determination sequence to the memory; and a decoding circuit configured to read the compressed data sequence and the validity determination sequence from the memory, and determine a bit in the bit string of the compressed data sequence set for transmission to a neural network circuit, based on the validity determination sequence, such that the neural network circuit omits an operation with respect to non-consecutive invalid bits.

公开(公告)号：US12175299B2

公开(公告)日：2024-12-24

申请号：US17223139

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jae-Eon Jo ,  Hyung-Dal Kwon ,  Hanmin Park ,  Jaehyeong Sim ,  Seung Wook Lee

IPC: G06F9/50 ,  G06F1/3237 ,  G06F9/48 ,  G06N3/045 ,  G06N3/063

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

公开(公告)号：US11960855B2

公开(公告)日：2024-04-16

申请号：US17102884

申请日：2020-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal Kwon ,  Hanmin Park ,  Seungwook Lee ,  Jae-Eon Jo

IPC: G06F7/544 ,  G06F7/57 ,  G06N3/08

CPC classification number: G06F7/5443 ,  G06F7/57 ,  G06N3/08

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

公开(公告)号：US11899741B2

公开(公告)日：2024-02-13

申请号：US16856380

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal Kwon ,  Seung Wook Lee

IPC: G06F17/15 ,  G06F7/544 ,  G06F17/14 ,  G06F17/16 ,  G06F13/28 ,  H03H17/02

CPC classification number: G06F17/15 ,  G06F7/5443 ,  G06F13/28 ,  G06F17/14 ,  G06F17/16 ,  H03H17/0213

Abstract: A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.

公开(公告)号：US10355737B2

公开(公告)日：2019-07-16

申请号：US16180871

申请日：2018-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal Kwon ,  Gyeong Min Ha ,  Ho-Suk Na

IPC: H04B1/40 ,  H04B1/401 ,  G06F3/041 ,  H04L12/40 ,  H04B1/3888 ,  H04B7/26

Abstract: A touch screen controller (TSC) includes: a front end circuit configured to send a control signal to a touch panel and to receive a touch signal from the touch panel; an algorithm processing circuit configured to process source data generated based on the touch signal according to a predetermined algorithm; a memory configured to store the source data and result data obtained as a result of processing the source data at the algorithm processing circuit; and a bus configured to transfer data among the front end circuit, the algorithm processing circuit, and the memory. The algorithm processing circuit includes: a buffer configured to temporarily store the source data or the result data and shared by at least two circuits; and a special function register (SFR) configured to store a setting value necessary for an operation of the algorithm processing circuit.

公开(公告)号：US11886887B2

公开(公告)日：2024-01-30

申请号：US17316893

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Sunghoon Son ,  Hyung-Dal Kwon

IPC: G06F9/4401 ,  G06F13/28 ,  G06F8/71 ,  G06F8/654

CPC classification number: G06F9/4416 ,  G06F8/654 ,  G06F8/71 ,  G06F9/4418 ,  G06F13/28

Abstract: An operating method of an electronic device including controllers includes updating, by a first-level controller of the controllers, a first-level firmware of the the first-level controller, writing, by the first-level controller, a second-level firmware to one of second-level controllers of the controllers having a lower level than the first-level controller, booting, by the one of the second-level controllers, by performing a reset operation, verifying, by the first-level controller or the booted second-level controller, whether there is a target second-level controller with out-of-date firmware, and writing, by the first-level controller or the booted second-level controller in response to a result of the verifying, the second-level firmware to the target second-level controller.

公开(公告)号：US11580393B2

公开(公告)日：2023-02-14

申请号：US16900007

申请日：2020-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal Kwon

IPC: G06N3/08 ,  G06N3/04 ,  H03M7/30

Abstract: A neural network deep learning data control apparatus includes: a memory; an encoding circuit configured to receive a data sequence, generate a compressed data sequence in which consecutive invalid bits in a bit string of the data sequence are compressed into a single bit of the compressed data sequence, generate a validity determination sequence indicating a valid bit and an invalid bit in a bit string of the compressed data sequence, and write the compressed data sequence and the validity determination sequence to the memory; and a decoding circuit configured to read the compressed data sequence and the validity determination sequence from the memory, and determine a bit in the bit string of the compressed data sequence set for transmission to a neural network circuit, based on the validity determination sequence, such that the neural network circuit omits an operation with respect to non-consecutive invalid bits.

公开(公告)号：US10141972B2

公开(公告)日：2018-11-27

申请号：US15393501

申请日：2016-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal Kwon ,  Gyeong Min Ha ,  Ho-Suk Na

IPC: H04B1/40 ,  H04B1/401 ,  H04L12/40 ,  H04B7/26 ,  G06F3/041

Abstract: A touch screen controller (TSC) includes: a front end circuit configured to send a control signal to a touch panel and to receive a touch signal from the touch panel; an algorithm processing circuit configured to process source data generated based on the touch signal according to a predetermined algorithm; a memory configured to store the source data and result data obtained as a result of processing the source data at the algorithm processing circuit; and a bus configured to transfer data among the front end circuit, the algorithm processing circuit, and the memory. The algorithm processing circuit includes: a buffer configured to temporarily store the source data or the result data and shared by at least two circuits; and a special function register (SFR) configured to store a setting value necessary for an operation of the algorithm processing circuit.

公开(公告)号：US12236336B2

公开(公告)日：2025-02-25

申请号：US17168457

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal Kwon

IPC: G06N3/063 ,  G06F7/544 ,  G06F9/38

Abstract: Disclosed is a method and apparatus with deep learning operations. A deep learning apparatus includes a processor, configured to support a plurality of different operation modes, including a systolic array having a plurality of multiplier accumulator (MAC) units, and a control circuit configured to respectively control, for each the plurality of different operation modes, select operations of the plurality of MAC units and data movements among the plurality of MAC units.