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    Semiconductor memory device, controller, and memory system
    1.
    发明授权
    Semiconductor memory device, controller, and memory system 有权

    公开(公告)号：US10824507B2

    公开(公告)日：2020-11-03

    申请号：US16372047

    申请日：2019-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung Kyu Lee ,  Jun Jin Kong ,  Ki Jun Lee ,  Sung Hye Cho ,  Dae Hyun Kim ,  Yong Gyu Chu

    IPC: G06F11/10 ,  H03M13/29 ,  G11C29/52

    Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
    4.
    发明授权
    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same 有权
    具有多个子存储单元阵列的半导体存储器件和包括其的存储器系统

    公开(公告)号：US09384092B2

    公开(公告)日：2016-07-05

    申请号：US14300289

    申请日：2014-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae Hyun Kim ,  Seung Jun Bae ,  Young Soo Sohn ,  Tae Young Oh ,  Won Jin Lee

    IPC: G11C29/42 ,  G06F11/10 ,  G11C7/08 ,  G11C7/06 ,  G11C29/54 ,  G11C11/4091 ,  G11C11/419

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/419

    Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

    Abstract translation: 半导体存储器件包括： 存储单元阵列，包括存储具有第一特性的第一数据的第一子存储单元阵列和存储具有与第一特性不同的第二特性的第二数据的第二子存储单元阵列;第一外围电路， 子存储器单元阵列，以执行指向第一子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个，以及仅与第二子存储单元阵列可操作地相关联的第二外围电路， 执行指向第二子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20230006046A1

    公开(公告)日：2023-01-05

    申请号：US17941828

    申请日：2022-09-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghwan HUH ,  Dongchan Kim ,  Dae Hyun Kim ,  Euiju Kim ,  Jisoo Lee

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

    Abstract: A semiconductor device includes a substrate, a gate trench in the substrate, a gate insulating film in the gate trench, a titanium nitride (TiN)-lower gate electrode film on the gate insulating film, the titanium nitride (TiN)-lower gate electrode film including a top surface, a first side surface, and a second side surface opposite the first side surface, a polysilicon-upper gate electrode film on the titanium nitride (TiN)-lower gate electrode film, and a gate capping film on the polysilicon-upper gate electrode film. A center portion of the top surface of the titanium nitride (TiN)-lower gate electrode film overlaps a center portion of the polysilicon-upper gate electrode film in a direction that is perpendicular to a top surface of the substrate, and each of the first side surface and the second side surface of the titanium nitride (TiN)-lower gate electrode film is connected to the gate insulating film.

    Semiconductor device and method of forming the same
    9.
    发明授权
    Semiconductor device and method of forming the same 有权

    公开(公告)号：US11462623B2

    公开(公告)日：2022-10-04

    申请号：US17222474

    申请日：2021-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghwan Huh ,  Dongchan Kim ,  Dae Hyun Kim ,  Euiju Kim ,  Jisoo Lee

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

    Abstract: A semiconductor device includes a substrate including an active region, a gate trench disposed in the substrate and crossing the active region; a gate dielectric layer disposed in the gate trench; a first gate electrode disposed on the gate dielectric layer and including center and edge portions; a second gate electrode disposed on the first gate electrode; a gate capping insulating layer disposed on the second gate electrode and filling the gate trench; and first and second impurity regions disposed in the substrate opposite to each other with respect to the gate trench. A top surface of each of the center and edge portions contacts a bottom surface of the second gate electrode. The top surface of the second gate electrode is concave. The bottom surface of the gate capping insulating layer is convex, and a side surface of the gate capping insulating layer contacts the gate dielectric layer.

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