公开(公告)号：US12046599B2

公开(公告)日：2024-07-23

申请号：US17522051

申请日：2021-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Jongchul Park ,  Hyunho Jung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having first and second active regions. A first active pattern is on the first active region and includes first source/drain patterns and a first channel pattern therebetween. A second active pattern is on the second active region and includes second source/drain patterns and a second channel pattern therebetween. A gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern. A gate cutting pattern is between the first and second gate electrodes and separates the first and second gate electrodes from each other. A pair of gate spacers is on opposite sidewalls of the first gate electrode extending along opposite sidewalls of the gate cutting pattern towards the second gate electrode. The gate cutting pattern includes first to third parts having maximum widths that increase from the first to the third part.

公开(公告)号：US12142607B2

公开(公告)日：2024-11-12

申请号：US17713834

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

公开(公告)号：US20220406775A1

公开(公告)日：2022-12-22

申请号：US17713834

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

公开(公告)号：US10192966B2

公开(公告)日：2019-01-29

申请号：US15692560

申请日：2017-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunho Jung ,  Jeongyun Lee ,  Taesoon Kwon ,  Kyungseok Min ,  Geumjung Seong ,  Bora Lim ,  A-Reum Ji ,  Seungsoo Hong

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device can include a first active pattern on a substrate, the first active pattern including a plurality of first active regions that protrude from the substrate. A second active pattern can be on the substrate including a plurality of second active regions that protrude from the substrate. A first gate electrode can include an upper portion that extends over the first active pattern at a first height and include a recessed portion that extends over the first active pattern at a second height that is lower than the first height of the first gate electrode. A second gate electrode can include an upper portion that extends over the second active pattern at a first height and include a recessed portion that extends over the second active pattern at a second height that is lower than the first height of the second gate electrode. An insulation pattern can be located between, and directly adjacent to, the recessed portion of the first gate electrode and the recessed portion of the second gate electrode, the insulation pattern electrically isolating the first and second gate electrodes from one another.