公开(公告)号：US10332898B2

公开(公告)日：2019-06-25

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US11290201B2

公开(公告)日：2022-03-29

申请号：US16991744

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haechul Lee ,  Myungjoon Shim ,  Bora Lim ,  Sungyoon Cho

IPC: H04J11/00 ,  H04W92/18

Abstract: An operation method of an electronic device including: dividing a cell search period into a plurality of partial detection ranges based on the number of partial buffers and a size of the partial buffer; obtaining a first correlation detection information based on a first synchronization signal, while temporarily storing first signals in a first partial buffer among the partial buffers, in which the first signals are received during a first partial detection range among the plurality of partial detection ranges; and obtaining a second correlation detection information for the first signals based on the first correlation detection information and a second synchronization signal, during a second partial detection range among the plurality of partial detection ranges and obtaining the first correlation detection information for second signals based on the first synchronization signal, while temporarily storing the second signals received during the second partial detection range in a second partial buffer.

公开(公告)号：US11218239B2

公开(公告)日：2022-01-04

申请号：US16685354

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyoon Cho ,  Joohyun Do ,  Myungjoon Shim ,  Haechul Lee ,  Bora Lim ,  Dahae Chong ,  Seungjoong Hwang

IPC: H04J11/00 ,  H04W72/00 ,  H04W56/00

Abstract: An operating method of a terminal performing a cell search using first and second memories for buffering input samples includes detecting a first primary synchronization signal (PSS) group from a first input sample group while buffering the first input sample group in the first memory in a first interval. While buffering a second input sample group in the second memory in a second interval following the first interval, the method detects a second PSS group from the second input sample group, and a first secondary synchronization signal (SSS) group corresponding to the first PSS group from the first input sample group. While buffering a third input sample group in the first memory in a third interval following the second interval, the method detects a third PSS group from the third input sample group, and a second SSS group corresponding to the second PSS group from the second input sample group.

公开(公告)号：US20190244965A1

公开(公告)日：2019-08-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US10861860B2

公开(公告)日：2020-12-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US10192966B2

公开(公告)日：2019-01-29

申请号：US15692560

申请日：2017-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunho Jung ,  Jeongyun Lee ,  Taesoon Kwon ,  Kyungseok Min ,  Geumjung Seong ,  Bora Lim ,  A-Reum Ji ,  Seungsoo Hong

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device can include a first active pattern on a substrate, the first active pattern including a plurality of first active regions that protrude from the substrate. A second active pattern can be on the substrate including a plurality of second active regions that protrude from the substrate. A first gate electrode can include an upper portion that extends over the first active pattern at a first height and include a recessed portion that extends over the first active pattern at a second height that is lower than the first height of the first gate electrode. A second gate electrode can include an upper portion that extends over the second active pattern at a first height and include a recessed portion that extends over the second active pattern at a second height that is lower than the first height of the second gate electrode. An insulation pattern can be located between, and directly adjacent to, the recessed portion of the first gate electrode and the recessed portion of the second gate electrode, the insulation pattern electrically isolating the first and second gate electrodes from one another.

公开(公告)号：US10026809B1

公开(公告)日：2018-07-17

申请号：US15662248

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung Seong ,  JeongYun Lee ,  SeungSoo Hong ,  KyungSeok Min ,  SeungJu Park ,  Youngmook Oh ,  Bora Lim

IPC: H01L29/76 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

Abstract: Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.