Semiconductor devices
    3.
    发明授权

    公开(公告)号:US12062662B2

    公开(公告)日:2024-08-13

    申请号:US18142210

    申请日:2023-05-02

    CPC classification number: H01L27/0924 H01L29/7851

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

    SEMICONDUCTOR DEVICES
    4.
    发明公开

    公开(公告)号:US20230275091A1

    公开(公告)日:2023-08-31

    申请号:US18142210

    申请日:2023-05-02

    CPC classification number: H01L27/0924 H01L29/7851

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

    SEMICONDUCTOR DEVICES
    5.
    发明申请

    公开(公告)号:US20220115375A1

    公开(公告)日:2022-04-14

    申请号:US17348962

    申请日:2021-06-16

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

    Semiconductor devices
    6.
    发明授权

    公开(公告)号:US11670638B2

    公开(公告)日:2023-06-06

    申请号:US17348962

    申请日:2021-06-16

    CPC classification number: H01L27/0924 H01L29/7851

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

Patent Agency Ranking