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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180374926A1

    公开(公告)日：2018-12-27

    申请号：US15861949

    申请日：2018-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DONGSOO LEE ,  WONKEUN CHUNG ,  HOONJOO NA ,  SUYOUNG BAE ,  JAEYEOL SONG ,  JONGHAN LEE ,  HYUNGSUK JUNG ,  SANGJIN HYUN

    IPC: H01L29/49 ,  H01L29/36

    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406914A1

    公开(公告)日：2022-12-22

    申请号：US17691680

    申请日：2022-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JAEHYUN LEE ,  JONGHAN LEE ,  HYUNGKOO KANG ,  JONGHOON BAEK

    IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49

    Abstract: A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

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