公开(公告)号：US20180374926A1

公开(公告)日：2018-12-27

申请号：US15861949

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGSOO LEE ,  WONKEUN CHUNG ,  HOONJOO NA ,  SUYOUNG BAE ,  JAEYEOL SONG ,  JONGHAN LEE ,  HYUNGSUK JUNG ,  SANGJIN HYUN

IPC: H01L29/49 ,  H01L29/36

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20160358921A1

公开(公告)日：2016-12-08

申请号：US15017789

申请日：2016-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： MOONKYU PARK ,  HOONJOO NA ,  JAEYEOL SONG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L27/02

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

Abstract translation: 半导体器件包括具有第一区域和第二区域的半导体衬底以及第一区域上的第一栅极图案和第二区域上的第二栅极图案。 第一栅极图案包括第一区域上的第一栅极绝缘图案，第一栅极绝缘图案上的第一栅极栅极图案和第一栅极阻挡图案上的第一功函数金属图案。 第二栅极图案包括第二区域上的第二栅极绝缘图案，第二栅极绝缘图案上的第二栅极栅极图案，以及第二栅极阻挡图案上的第二功函数金属图案。 第一栅极阻挡图案包括不同于第二栅极阻挡图案的金属材料。

公开(公告)号：US20200098599A1

公开(公告)日：2020-03-26

申请号：US16397552

申请日：2019-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEYEONG KIM ,  MINSOO HAN ,  JUN HYUNG KIM ,  HOONJOO NA ,  KWANGJIN MOON

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/687

Abstract: A substrate bonding apparatus includes a lower chuck that receives a lower substrate and an upper chuck disposed above the lower chuck. An upper substrate is fixed to the upper chuck. The upper chuck and the lower chuck bond the upper substrate to the lower substrate. The upper chuck has an upper convex surface toward the lower chuck. The upper convex surface includes a plurality of first ridges and a plurality of first valleys disposed alternately along an azimuthal direction.