INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND METHODS OF FORMING THE SAME

    公开(公告)号:US20230142609A1

    公开(公告)日:2023-05-11

    申请号:US17574043

    申请日:2022-01-12

    CPC classification number: H01L29/42392 H01L29/167 H01L27/0928 H01L21/823857

    Abstract: Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

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