公开(公告)号：US20170162675A1

公开(公告)日：2017-06-08

申请号：US15361516

申请日：2016-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hwan YIM ,  Yeon-Tack RYU ,  Joo-Cheol HAN ,  Ja-Eung KOO ,  No-Ul KIM ,  Ho-Young KIM ,  Bo-Un YOON

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

公开(公告)号：US20200027842A1

公开(公告)日：2020-01-23

申请号：US16383816

申请日：2019-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae LEE ,  Seung-Hoon CHOI ,  Min-Chan GWAK ,  Ja-Eung KOO ,  Sang-Hyun PARK

IPC: H01L23/544 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

公开(公告)号：US20170040436A1

公开(公告)日：2017-02-09

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae LEE ,  Ja-Eung KOO ,  Ho-Young KIM ,  Yeong-Bong PARK ,  Il-Su PARK ,  Bo-Un YOON ,  Il-Young YOON ,  Youn-Su HA

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract translation: 一种用于制造半导体器件的方法可以包括在衬底的第一区域中形成具有第一阈值电压的第一晶体管，在衬底的第二区域中形成具有小于第一阈值电压的第二阈值电压的第二晶体管，形成 在第三区域中的第三层间绝缘膜，并且平坦化第一晶体管，第二晶体管和第三层间绝缘膜。 第一晶体管可以包括具有第一高度的第一栅极电极和具有第一高度的第一层间绝缘膜，并且第二晶体管可以包括具有比第一高度短的第二高度的第二栅极电极和第二层间绝缘膜， 第二高度。 第三层间绝缘膜可以具有第一高度。