公开(公告)号：US20170040436A1

公开(公告)日：2017-02-09

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae LEE ,  Ja-Eung KOO ,  Ho-Young KIM ,  Yeong-Bong PARK ,  Il-Su PARK ,  Bo-Un YOON ,  Il-Young YOON ,  Youn-Su HA

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract translation: 一种用于制造半导体器件的方法可以包括在衬底的第一区域中形成具有第一阈值电压的第一晶体管，在衬底的第二区域中形成具有小于第一阈值电压的第二阈值电压的第二晶体管，形成 在第三区域中的第三层间绝缘膜，并且平坦化第一晶体管，第二晶体管和第三层间绝缘膜。 第一晶体管可以包括具有第一高度的第一栅极电极和具有第一高度的第一层间绝缘膜，并且第二晶体管可以包括具有比第一高度短的第二高度的第二栅极电极和第二层间绝缘膜， 第二高度。 第三层间绝缘膜可以具有第一高度。

公开(公告)号：US20170040208A1

公开(公告)日：2017-02-09

申请号：US15142043

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon CHOI ,  Ho-Young KIM ,  Gi-Gwan PARK ,  Hyun-Kyung BAE ,  Bo-Un YOON ,  Il-Young YOON

IPC: H01L21/768

CPC classification number: H01L21/7684 ,  B24B37/042 ,  H01L21/67219 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/41791

Abstract: A method of forming a plug and manufacturing a semiconductor device, a polishing chamber, and a semiconductor device, the method of forming a plug including forming an opening in an insulating interlayer pattern on a substrate; forming a metal layer to fill the opening; performing a first CMP process during a first time period until a top surface of the insulating interlayer pattern is exposed while pressing the substrate onto a first polishing pad to polish the metal layer; performing a second CMP process during a second time period while pressing the substrate onto a second polishing pad to polish the metal layer and the insulating interlayer pattern, so that a metal plug is formed in the insulating interlayer pattern; and performing a first cleaning process on the second polishing pad while keeping the substrate spaced apart from the second polishing pad on the second platen.

Abstract translation: 一种形成插头并制造半导体器件，抛光室和半导体器件的方法，包括在衬底上形成绝缘层间图案中的开口的形成插头的方法; 形成金属层以填充开口; 在第一时间段内执行第一CMP处理直到绝缘层间图案的顶表面暴露，同时将基板压在第一抛光垫上以抛光金属层; 在第二时间段内执行第二CMP处理，同时将衬底按压到第二抛光垫上以抛光金属层和绝缘层间图案，从而在绝缘层间图案中形成金属插塞; 以及在所述第二台板上保持与所述第二抛光垫间隔开的所述基板的同时对所述第二抛光垫进行第一清洁处理。

公开(公告)号：US20150364574A1

公开(公告)日：2015-12-17

申请号：US14579627

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn KIM ,  Dong-Hyun ROH ,  Sang-Duk PARK ,  Il-Young YOON ,  Jeong-Nam HAN ,  Jong-Mil YOUN

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/66636

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate insulation layer pattern, a dummy gate electrode and a gate mask sequentially stacked are formed on a substrate. An interlayer insulating layer including tonen silazane (TOSZ) is formed on the substrate to cover the dummy gate structure. An upper portion of the interlayer insulating layer is planarized until a top surface of the gate mask is exposed to form an interlayer insulating layer pattern. The exposed gate mask, and the dummy gate electrode and the dummy gate insulation layer pattern under the gate mask are removed to form an opening exposing a top surface of the substrate. The dummy gate insulation layer pattern is removed using an etchant including hydrogen fluoride (HF), but the interlayer insulating layer pattern remains. A gate structure is formed to fill the opening.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成包括虚拟栅极绝缘层图案，虚拟栅极电极和栅极掩模的虚拟栅极结构。 在基板上形成包含蒙片硅氮烷（TOSZ）的层间绝缘层，以覆盖虚拟栅极结构。 层间绝缘层的上部被平坦化，直到露出栅极掩模的顶表面以形成层间绝缘层图案。 除去栅极掩模下的露出的栅极掩模，伪栅极电极和伪栅极绝缘层图案，以形成露出衬底顶表面的开口。 使用包括氟化氢（HF）的蚀刻剂去除伪栅极绝缘层图案，但是残留层间绝缘层图案。 形成浇口结构以填充开口。