公开(公告)号：US20150357298A1

公开(公告)日：2015-12-10

申请号：US14637545

申请日：2015-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Gwon JANG ,  Jong-Ho LEE ,  Ae-Nee JANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/2511 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1441 ,  H01L2224/03

Abstract: A semiconductor chip includes a semiconductor chip die having a first surface and a second surface facing the first surface, a connection pad on the first surface of the semiconductor chip die, and a redistribution pad arranged on the first surface of the semiconductor chip die and electrically connected to the connection pad and including an end portion having a concave-convex structure and extended to a lateral surface of the semiconductor chip die.

Abstract translation: 半导体芯片包括具有第一表面和面向第一表面的第二表面的半导体芯片裸片，半导体芯片裸片的第一表面上的连接焊盘和布置在半导体芯片裸片的第一表面上的再分布焊盘， 连接到连接焊盘并且包括具有凹凸结构并延伸到半导体芯片裸片的侧表面的端部。

公开(公告)号：US20170069828A1

公开(公告)日：2017-03-09

申请号：US15227953

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-Woo LEE ,  Eun-Seok SONG ,  Young-Jae KIM ,  Jae-Gwon JANG

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L23/552 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface. The bottom surface of the bonding portion contacts the first bonding surface to form a first contact surface. The top surface of the bonding portion contacts the second bonding surface to form a second contact surface. An area of the second contact surface is larger than an area of the second end surface.

Abstract translation: 在一个实施例中，一种半导体器件，包括：衬底，其包括布线层，设置在衬底上并与布线层电隔离的第一导电屏蔽层，第一导电屏蔽层包括第一接合表面和第一端面， 所述第一接合表面，设置在所述第一导电屏蔽层上的半导体芯片，设置在所述第一导电屏蔽层上以覆盖所述半导体芯片的成型构件，设置在所述第一导电屏蔽层和所述模制构件上方的第二导电屏蔽层， 第二导电屏蔽层，包括从第二接合表面延伸的第二接合表面和第二端表面，以及设置在第一和第二接合表面之间的接合部分，接合部分包括顶表面和与顶表面相对的底表面 。 接合部分的底表面接触第一接合表面以形成第一接触表面。 接合部分的顶表面接触第二接合表面以形成第二接触表面。 第二接触面的面积大于第二端面的面积。