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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210233897A1

    公开(公告)日：2021-07-29

    申请号：US17018324

    申请日：2020-09-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-Nee JANG ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250157967A1

    公开(公告)日：2025-05-15

    申请号：US18941796

    申请日：2024-11-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-Nee JANG ,  Haseob SEONG

    IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00

    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip thereon. The first semiconductor chip includes upper bonding pads at an upper portion thereof. The second semiconductor chip includes lower bonding pads at a lower portion thereof. The first semiconductor chip and the second semiconductor chip are connected through direct contact between the upper bonding pads and lower bonding pads. The upper bonding pads include edge bonding pads on an edge region of the first semiconductor chip and arranged in a first direction parallel to an edge of the first semiconductor chip. The edge bonding pads include a first edge pad and a second edge pad disposed adjacent to each other. The each of the first and second edge pads is one of a power pad, a ground pad, and a dummy pad, and the first and second edge pads are of the same type.

    SYSTEM-IN-PACKAGE MODULE
    6.
    发明申请
    SYSTEM-IN-PACKAGE MODULE 有权

    公开(公告)号：US20220328454A1

    公开(公告)日：2022-10-13

    申请号：US17853140

    申请日：2022-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-Nee JANG ,  Kyung Suk OH ,  Eunseok SONG ,  Seung-Yong CHA

    IPC: H01L25/065 ,  H01L25/18

    Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210296200A1

    公开(公告)日：2021-09-23

    申请号：US17340197

    申请日：2021-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-Nee JANG ,  Seung-Duk BAEK ,  Tae-Heon KIM

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250149475A1

    公开(公告)日：2025-05-08

    申请号：US18802580

    申请日：2024-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min Seung JI ,  Ha Seob SEONG ,  Hyeon Min LEE ,  Ae-Nee JANG

    IPC: H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/528 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

    Abstract: A semiconductor includes a first semiconductor chip, and a second semiconductor chip provided on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate including a first front side and a first back side, and a first back-side bonding layer including a first back-side bonding insulating film, and a first back-side bonding pad, wherein the second semiconductor chip includes a second semiconductor substrate including a second front side that faces the first back side and a second back side, and a second front-side bonding layer including a second front-side bonding insulating film bonded to the first back-side bonding insulating film. A side of the first semiconductor chip includes a plurality of first recesses, which are arranged along a vertical direction, and a second recess, which partially exposes a bottom surface of the second front-side bonding layer between the second front-side bonding layer and the first recesses.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220208743A1

    公开(公告)日：2022-06-30

    申请号：US17696157

    申请日：2022-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-Nee JANG ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

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