-
公开(公告)号：US08947935B2
公开(公告)日：2015-02-03
申请号：US13835780
申请日：2013-03-15
Applicant: SAMSUNG Electronics Co., Ltd.
Inventor： Eui-Seung Kim , Ji-Sung Kim
CPC classification number: G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/28
Abstract: An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.
Abstract translation: 集成包括存储器单元，连接到存储单元的位线，在预充电位线的预充电操作期间将位线升高到升压电压的升压电路，以及连接在位之间的调节电路 线路和输出端子，并根据位线的电压确定输出端子的逻辑电平。
-
公开(公告)号：US11062776B2
公开(公告)日：2021-07-13
申请号：US16731288
申请日：2019-12-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Jin Shin , Ji-Sung Kim , Ho Young Shin , Myeong Hee Oh
Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells that are programmed based on a high voltage, a high voltage generator to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator to generate the pumping clock, a high voltage detector to generate a detection signal by comparing an adjustment voltage with a reference voltage, a programming current controller to adjust a programming current flowing through each of selected memory cells of the plurality of memory cells; and a control logic to adjust a frequency of the pumping clock and a current driving capability of the programming current based on the detection signal during a programming period with respect to the selected memory cells. The detection signal includes information indicating whether the high voltage reaches to a target voltage.
-
Patent Agency Ranking
公开(公告)号：US09001588B2
公开(公告)日：2015-04-07
申请号：US13715471
申请日：2012-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eui-Seung Kim , Ji-Sung Kim , SeEun O
Abstract: A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.
Abstract translation: 提供了一种非易失性半导体存储器件的读出放大器电路。 感测放大器电路包括参考电压发生器，感测电压发生器和比较器。 感测电压发生器根据流过数据线的电流将感测电压输出到感测节点。 向数据线提供电流的负载晶体管直接连接到钳位节点。 负载晶体管包括在电流镜电路中。 在读取操作中，执行低电压驱动操作并且适当地控制感测速度和功耗。
-
公开(公告)号：US20240389348A1
公开(公告)日：2024-11-21
申请号：US18417089
申请日：2024-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungmin Park , Hanjin Lim , Ji-Sung Kim , Hyungsuk Jung
Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a lower electrode, a dielectric layer on the lower electrode, an upper electrode on the dielectric layer, and a defect preventing layer between the lower electrode and the upper electrode. The defect preventing layer includes at least one of a first defect preventing layer between the lower electrode and the dielectric layer or a second defect preventing layer between the upper electrode and the dielectric layer. The dielectric layer includes a ferroelectric layer that includes at least one of a ferroelectric material or an anti-ferroelectric material. The ferroelectric layer includes a polarization region and a non-polarization region surrounded by the polarization region.
-
5.发明授权公开(公告)号：US12041188B2
公开(公告)日：2024-07-16
申请号：US17394613
申请日：2021-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoyoung Shin , Sung Ung Kwak , Ji-Sung Kim , Shin-Wuk Kang
CPC classification number: H04L9/3278 , G11C7/06 , G11C8/10 , H03M1/662 , H04L9/0866
Abstract: A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.
-
公开(公告)号：US10957395B2
公开(公告)日：2021-03-23
申请号：US16828099
申请日：2020-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoyoung Shin , Ji-Sung Kim , Hyun-Jin Shin
Abstract: A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time.
-
公开(公告)号：US20130201761A1
公开(公告)日：2013-08-08
申请号：US13715471
申请日：2012-12-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eui-Seung KIM , Ji-Sung Kim , SeEun O
IPC: G11C16/28
Abstract: A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.
Abstract translation: 提供了一种非易失性半导体存储器件的读出放大器电路。 感测放大器电路包括参考电压发生器，感测电压发生器和比较器。 感测电压发生器根据流过数据线的电流将感测电压输出到感测节点。 向数据线提供电流的负载晶体管直接连接到钳位节点。 负载晶体管包括在电流镜电路中。 在读取操作中，执行低电压驱动操作并且适当地控制感测速度和功耗。
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
