公开(公告)号：US20250040132A1

公开(公告)日：2025-01-30

申请号：US18626728

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeseop Choi ,  Byunghoon Kim ,  Junho Kim ,  Youngwook Park ,  Jiho Park ,  Jungwoo Lee ,  Jihyun Hwang ,  Minho Choi

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, where the substrate includes at least one first active pattern in the cell region and a second active pattern in the core region; a first trench defined by the at least one first active pattern; and a second trench defined by the second active pattern, where an inner sidewall of the first trench defines first recesses that extend into the at least one first active pattern, an inner sidewall of the second trench defines second recesses that extend into the second active pattern, a distance between two adjacent first recesses from among the first recesses in the vertical direction corresponds to a first height, a distance between two adjacent second recesses from among the second recesses in the vertical direction corresponds to a second height.

公开(公告)号：US12156477B2

公开(公告)日：2024-11-26

申请号：US17314320

申请日：2021-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Park

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

公开(公告)号：US11017989B2

公开(公告)日：2021-05-25

申请号：US16127452

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Park ,  Jeonghee Park ,  Changyup Park

IPC: H01J37/34 ,  H01J37/32 ,  H01L27/24 ,  H01L45/00

Abstract: Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.

公开(公告)号：US11482670B2

公开(公告)日：2022-10-25

申请号：US16909218

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Park ,  Kwangmin Park ,  Jeonghee Park ,  Changyup Park ,  Sukhwan Chung

IPC: H01L45/00

Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 μs to about 54 μs.

公开(公告)号：US11387410B2

公开(公告)日：2022-07-12

申请号：US16800123

申请日：2020-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghee Park ,  Kwangmin Park ,  Jiho Park ,  Gyuhwan Oh ,  Jungmoo Lee ,  Hideki Horii

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

公开(公告)号：US20240395615A1

公开(公告)日：2024-11-28

申请号：US18631548

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokwon Kim ,  Bongjin Kuh ,  Sukhoon Kim ,  Jiho Park ,  Sanghyeok Yu ,  Yongho Ha ,  Musarrat Hasan

IPC: H01L21/768 ,  C23C16/34 ,  C23C16/505

Abstract: A method of manufacturing a semiconductor device includes forming a substrate including a structure having a first region and a contact hole exposing the first region, loading the substrate into a process chamber, repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first time duration and not applying the RF plasma power to the process gas for a second time duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, and thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure, performing a removal process of removing at least a portion of the sidewall material layer in the process chamber, and unloading the substrate from the process chamber after performing the removal process.

公开(公告)号：US11574956B2

公开(公告)日：2023-02-07

申请号：US17314638

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Park ,  Kwangmin Park ,  Wonjun Park ,  Jeonghee Park ,  Changyup Park ,  Hwasung Chae

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

公开(公告)号：US20220085105A1

公开(公告)日：2022-03-17

申请号：US17314638

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Park ,  Kwangmin Park ,  Wonjun Park ,  Jeonghee Park ,  Changyup Park ,  Hwasung Chae

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

公开(公告)号：US10892410B2

公开(公告)日：2021-01-12

申请号：US16459637

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghee Park ,  Jiho Park ,  Changyup Park ,  Dongho Ahn

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.

公开(公告)号：US11600776B2

公开(公告)日：2023-03-07

申请号：US17033460

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Jung ,  Kyoung Sun Kim ,  Jeonghee Park ,  Jiho Park ,  Changyup Park

IPC: H01L45/00 ,  H01J37/32 ,  H01J37/34 ,  H01L27/24

Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.